verilog Examples and Free Source Code

What's included in a Verilog always @* sensitivity list?...

verilog system-verilog digital-logic

$readmemh syntax error for .mif file in Verilog HDL Intel Quartus Prime...

verilog system-verilog quartus

Getting XXX in the output IR REGISTER = XXXXX...

verilog

2 consecutive nonblocking assignments...

verilog system-verilog

Verilog issue with case/always statement...

verilog quartus

Verilog Error - Quartus II - Loop Must terminate within X iterations...

verilog system-verilog hdl

Why is my 8-bit counter stuck at 0 or 255?...

verilog counter quartus 8-bit cyclone

Verilog design: Where should my counter live?...

verilog

Assigning an ID number or code to Verilog module...

verilog

Are you allowed to have a module identifier be the same as the module type in Verilog?...

verilog system-verilog

My code does not move onto the next state even when the conditions are true...

verilog system-verilog hardware fpga hdl

How to wire up modules and pass value...

module verilog vivado

localparameters to make code generic to support different data widths...

verilog system-verilog fpga hdl

Why do I get an error calling a module in an always block?...

verilog

always block @posedge clock...

verilog system-verilog clock

ModelSim error: Instantiation of 'OR' failed...

verilog instantiation modelsim

How do I concatenate parameters and integers?...

verilog system-verilog quartus intel-fpga

Passing parameters to Verilog modules...

module verilog system-verilog fpga parameterization

Parameter inside a module inside a module...

verilog

Turning a 1-bit ALU into an 8-bit ALU...

verilog alu

Wrong output value in 8-bit ALU...

verilog modelsim alu

Red output running testbench on 4-bit ALU...

verilog system-verilog alu

Not outputting expected value in simple assignment...

verilog system-verilog

defparam for array of modules in verilog...

verilog

How to pass a string variable (not a string literal) to $dumpfile system task?...

verilog simulation system-verilog cadence

EDA Playground EPWave $dumpfile error: no vcd file found...

verilog system-verilog questasim edaplayground

Using wire or reg with input or output...

verilog system-verilog

Functional coverage problem using with instead of iff...

verilog system-verilog

How can I use $value$plusargs?...

verilog

Width independent functions...

verilog system-verilog