Search code examples
verilogsystem-verilogalu

Red output running testbench on 4-bit ALU

I'm trying to create a 4-bit ALU in Verilog that does multiplication, addition, BCD addition and concatenation. Here's my code so far:

module alu4bit(A,B,S,Y);

input [3:0] A, B;
input [1:0] S;
output [7:0] Y;
reg [7:0] Y;
wire [7:0] A0, A1, A2, A3;

multiplier4bit mod3(A,B,A3);

always @ (A,B,S)
begin
    case (S)
//      2'b00: 
//      2'b01: 
//      2'b10: 
        2'b11: Y = A3;
    
    endcase
end
endmodule

When trying to run a testbench setting S=3 for my multiplier and A=5, B=5, I get red lines with XXXXX for output. I think it has something to do with how I set up the outputs for the submodules. Should A0-3 be wires? I wish I had an error message to go by, but I'm kind of stuck at this point.

Solution

  • If you want your mux to be sensitive to the A3 signal, you need to add it to the sensitivity list:

    always @ (A,B,S,A3)

    Consider simplifying this to:

    always @*

    Refer to the IEEE Std 1800-2012, section "9.4.2.2 Implicit event_expression list".