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verilogsystem-veriloghardwarefpgahdl

My code does not move onto the next state even when the conditions are true


I have to display a message as well as a timer on the 7 segment LED. So I managed this by using a multiplexer and displayed the message "Hi" in one state and then after some time when the counter reaches 7500 it should stop displaying "Hi" and start showing the timer.

The problem is the it only displays "Hi" and does not move forward from there.

localparam [1:0]
                    idle = 2'b00,
                    starting = 2'b01,
                    time_it = 2'b10,
                    done = 2'b11;

reg state_reg, state_next;
reg [12:0] count_reg, count_next; //**change for simulation

always @ (posedge clock or posedge reset)
begin
    if(reset)
        begin 
            state_reg <= idle;
            count_reg <= 0;
        end
    else
        begin
            state_reg <= state_next;
            count_reg <= count_next;
        end
end
always @ (*)
begin
state_next = state_reg; //default state stays the same
count_next = count_reg;

case(state_reg)
    idle:
        begin
            //DISPLAY HI HERE
            sel = 2'b00;
            if(start)
            begin
                count_next = random; //get the random number from LFSR module
                state_next = starting;
            end
        end
    starting:
        begin
            if(count_next == 7500) 
            begin                           //and starting from 'rand' ensures a random delay
                outled = 1'b1; //turn on the led 
                state_next = time_it; //go to next state
            end

            else
                count_next = count_reg + 1; 
        end     
    time_it:
        begin
                sel = 2'b01; //start the timer
                state_next = done;                  
        end

    done:
        begin
            if(stop)
                begin
                    sel = 2'b10; //stop the timer
                    outled = 1'b0;
                end
        end

    endcase

case(sel)
    2'b00: //hi
    begin
        go_start = 0; //make sure timer module is off
        regd0 = 4'd12; 
        regd1 = 4'd10;
        regd2 = 4'd11;
        regd3 = 4'd12;
    end

    2'b01: //timer
    begin

        go_start = 1'b1; //enable start signal to start timer
        regd0 = reg_d0; //get values from stopwatch module
        regd1 = reg_d1; //get values from stopwatch module
        regd2 = reg_d2; //get values from stopwatch module
        regd3 = reg_d3; //get values from stopwatch module
    end

    2'b10: //stop timer
    begin
        go_start = 1'b0;
    end

    default:
    begin
        regd0 = 4'bx;
        regd1 = 4'bx;
        regd2 = 4'bx;
        regd3 = 4'bx;
    end
endcase         
end

Now in simulation, case stays at 00 and does not change even though it is told to do so in the time_it state. Since sel does not change go_start is not enabled and that is why the timer is never turned on. Why does it stay in sel=00?


Solution

  • Change your state regs from 1 to 2 bits wide:

    reg [1:0] state_reg, state_next;