verilog Examples and Free Source Code

Verilog parsing between logical and bitwise not (!/~)...

verilog system-verilog

Empty statement in verilog that requires a semicolon?...

verilog

Why the test bench module doesn't work as intended?...

verilog system-verilog test-bench

Simulation error in modelsim ACTEL6.6d: Illegal output or inout port connection...

simulation verilog modelsim

What is the reason for this error in ModelSim for my Verilog code? (string_literal.v(3): near "...

verilog modelsim

Cadence IUS simulator options...

verilog system-verilog cadence

Usage of 'begin/end' in design modules...

verilog system-verilog

How to fix this part-select error? Illegal operand for constant expression...

verilog system-verilog

How to implement HDMI pass-through on XILINX FPGA (Artix-7)...

verilog xilinx hdmi pass-through

Find minimum in array of numbers using Verilog for Priority Queue implementation...

arrays comparison verilog priority-queue system-verilog

LED Sequence on Basys3 with Verilog...

verilog system-verilog fpga vivado

Is it possible to create task within interface for specific modport?...

verilog system-verilog

Formal verification of synchronous FIFO with failing SystemVerilog assertion...

verilog system-verilog formal-verification system-verilog-assertions

Connecting output of 4-bit counter to Hex to 7-Seg decoder and creating testbench...

verilog system-verilog fpga

Weird Behavior of buffers in modelsim simulation...

verilog delay system-verilog modelsim test-bench

Why the memory content is not read? - verilog digital system design...

memory verilog system digital iverilog

I see undefined output sequences reading a memory in simulation...

memory verilog simulation test-bench iverilog

Vivado behavioral simulation results differ on different PCs, but synthesis results are the same...

verilog system-verilog vivado

Binary - BCD convertor works in sim, but does not work on FPGA...

verilog fpga synthesis register-transfer-level

Does the SystemVerilog standard allows mixing with Verilog files?...

verilog system-verilog

How to concatenate number (1'b1) and `define in a single statement...

concatenation verilog

Why am I not getting output after pass through design in testbench module driver and monitor?...

verilog system-verilog

Implicit net-type declaration and `default_nettype...

verilog system-verilog

Is there a way to condition on a type?...

verilog system-verilog parameterized-types

Error (10170): HDL syntax errors in Quartus (HDL)...

verilog system-verilog hdl quartus

Error opening .vcd file. No such file or directory...

verilog iverilog gtkwave

Ternary operation not working with unary operation...

verilog system-verilog

Reading parameter array through VPI...

arrays verilog system-verilog verilator vpi

Unexpected results in fixed-point conversion in Verilog...

verilog system-verilog iverilog

Trying to change Hexadecimal display to Signed Decimal in VCD...

verilog