Search code examples
Verilog parsing between logical and bitwise not (!/~)...


verilogsystem-verilog

Read More
Empty statement in verilog that requires a semicolon?...


verilog

Read More
Why the test bench module doesn't work as intended?...


verilogsystem-verilogtest-bench

Read More
Simulation error in modelsim ACTEL6.6d: Illegal output or inout port connection...


simulationverilogmodelsim

Read More
What is the reason for this error in ModelSim for my Verilog code? (string_literal.v(3): near "...


verilogmodelsim

Read More
Cadence IUS simulator options...


verilogsystem-verilogcadence

Read More
Usage of 'begin/end' in design modules...


verilogsystem-verilog

Read More
How to fix this part-select error? Illegal operand for constant expression...


verilogsystem-verilog

Read More
How to implement HDMI pass-through on XILINX FPGA (Artix-7)...


verilogxilinxhdmipass-through

Read More
Find minimum in array of numbers using Verilog for Priority Queue implementation...


arrayscomparisonverilogpriority-queuesystem-verilog

Read More
LED Sequence on Basys3 with Verilog...


verilogsystem-verilogfpgavivado

Read More
Is it possible to create task within interface for specific modport?...


verilogsystem-verilog

Read More
Formal verification of synchronous FIFO with failing SystemVerilog assertion...


verilogsystem-verilogformal-verificationsystem-verilog-assertions

Read More
Connecting output of 4-bit counter to Hex to 7-Seg decoder and creating testbench...


verilogsystem-verilogfpga

Read More
Weird Behavior of buffers in modelsim simulation...


verilogdelaysystem-verilogmodelsimtest-bench

Read More
Why the memory content is not read? - verilog digital system design...


memoryverilogsystemdigitaliverilog

Read More
I see undefined output sequences reading a memory in simulation...


memoryverilogsimulationtest-benchiverilog

Read More
Vivado behavioral simulation results differ on different PCs, but synthesis results are the same...


verilogsystem-verilogvivado

Read More
Binary - BCD convertor works in sim, but does not work on FPGA...


verilogfpgasynthesisregister-transfer-level

Read More
Does the SystemVerilog standard allows mixing with Verilog files?...


verilogsystem-verilog

Read More
How to concatenate number (1'b1) and `define in a single statement...


concatenationverilog

Read More
Why am I not getting output after pass through design in testbench module driver and monitor?...


verilogsystem-verilog

Read More
Implicit net-type declaration and `default_nettype...


verilogsystem-verilog

Read More
Is there a way to condition on a type?...


verilogsystem-verilogparameterized-types

Read More
Error (10170): HDL syntax errors in Quartus (HDL)...


verilogsystem-veriloghdlquartus

Read More
Error opening .vcd file. No such file or directory...


verilogiveriloggtkwave

Read More
Ternary operation not working with unary operation...


verilogsystem-verilog

Read More
Reading parameter array through VPI...


arraysverilogsystem-verilogverilatorvpi

Read More
Unexpected results in fixed-point conversion in Verilog...


verilogsystem-verilogiverilog

Read More
Trying to change Hexadecimal display to Signed Decimal in VCD...


verilog

Read More
BackNext