hdl Examples and Free Source Code

How can I schedule multiple inputs into an instantiated SystemVerilog module?...

verilog system-verilog hdl register-transfer-level

Elegant Way To Compress If/Elsif Statements into Single For Loop Statement in VHDL...

for-loop if-statement vhdl hdl

Why is "Set as Top-Level Entity" grayed out in quartus?...

verilog system-verilog hdl quartus

sel[1] and sel[2] have different bus widths error when trying to build and 8 way demux using the nan...

hdl nand2tetris

Verilog testbench code using gEDA and iVerilog...

verilog hdl iverilog

What is the difference between == and === in Verilog?...

verilog system-verilog hdl

Full Adder output always set to X...

system-verilog fpga hdl vivado

Verilog state machine state/next_state style...

verilog fpga hdl fsm

Dealing with arrays in HDL...

arrays syntax hdl bus nand2tetris

Why does my code keep triggering the default condition in case statement?...

case verilog hdl

HDLBits Dff8p - Reset not working when using a generate loop...

verilog hdl flip-flop

XXX on output ports...

verilog hdl xilinx-ise

Writing a counter to approximate a fraction with minimal error...

verilog hdl vga

SystemVerilog array of interfaces with unique parameters...

verilog system-verilog hdl

Verilog/SystemVerilog: "constant" function is considered non-constant...

verilog system-verilog hdl yosys verilator

Whether the execution order is guaranteed when the statements in fork join_any and the statements fo...

verilog system-verilog hdl

4 bit adder-subtractor in verilog...

verilog hdl iverilog

Assignment error: "Cannot assign to array"...

verilog hdl iverilog

'case item is unreachable' in Vivado synthesis process...

verilog fpga xilinx hdl vivado

Using Chisel Submodule within another Module: Cannot assign variables to the io input...

scala hdl chisel

if-else condition for custom libraries in VHDL...

vhdl fpga hdl vivado

VHDL when running ghdl -r my testbench is getting stuck after passing two values...

vhdl hdl test-bench alu ghdl

Parity checker in verilog only calculates a result once...

verilog hdl

Why does the Inferred Latch error occur during the synthesis process?...

verilog fpga xilinx hdl vivado

What is the nondeterminism in Verilog and simulator? Can control flow switch back and forth between ...

verilog system-verilog hdl

Vivado verilog 1 LUT cells form a combinatorial loop...

verilog hdl vivado soc

Difference between combinatoric signal dependant on clocked signal vs. registering it...

fpga hdl

What happens when multiple variables in Verilog's always block's sensitive list change at th...

verilog hdl

Syntax error when implementing a Mux gate in Nand2Tetris...

hardware hdl nand2tetris

Synchronizing Negative-Edge and Positive-Edge Triggered Flip-Flops in HDL...

verilog system-verilog hdl