defparam for array of modules in verilog

Question

I am trying to implement a parametrized special purpose memory with an array of my own defined register.

my_register:

module my_register(clk,
                   data_in,
                   write_enable,
                   equal);

parameter WORD_SIZE = 4;

input                           clk;
input       [WORD_SIZE - 1 : 0] data_in;
input                           write_enable;
output                          equal;

reg [WORD_SIZE - 1 : 0] register;

always @(posedge clk) begin
     if (write_enable)
         register = data_in;
end

assign equal = data_in ^ register;
endmodule

in the top module I have:

module my_memory(clk,
                 data_in,
                 write_enable, 
                 matches);

parameter MY_WORD_SIZE = 8;

input                                           clk;
input  [WORD_SIZE - 1 : 0]                      data_in;
input  [(2'b1 << MEMORY_ADDRESS_WIDTH) - 1 : 0] write_enable;
output [(2'b1 << MEMORY_ADDRESS_WIDTH) - 1 : 0] matches;

my_register memory [(2'b1 << MEMORY_ADDRESS_WIDTH) - 1 : 0] (clk, data_in, write_enable, matches);
endmodule

but the problem is I can't override the parameter WORD_SIZE of my_register in the top module.

I tried:

defparam memory.WORD_SIZE = MY_WORD_SIZE;

but this does't work and gives an error:

WORD_SIZE is not declared under prefix memory

Is there a way to override the parameter of an array of custom modules?

thanks in advance

Answer 1

You cannot use defparam to override an array of instances in one statement. You would have to repeat the defparam for each instance. But there is no need to use defparam statements in Verilog-2001 or SystemVerilog. You can pass parameters inline with instantiating statement.

module my_memory #(parameter MY_WORD_SIZE = 8) ( 
input                                           clk,
input  [WORD_SIZE - 1 : 0]                      data_in,
input  [(2'b1 << MEMORY_ADDRESS_WIDTH) - 1 : 0] write_enable,
output [(2'b1 << MEMORY_ADDRESS_WIDTH) - 1 : 0] matches
);

my_register #(.WORD_SIZE(MY_WORD_SIZE))
     memory [(2'b1 << MEMORY_ADDRESS_WIDTH) - 1 : 0] (clk, data_in, write_enable, matches);
endmodule