Search code examples
verilogsystem-verilogfpgahdl

localparameters to make code generic to support different data widths

I am currently designing Verilog logic that is generic so that I can modify the width of registers based on parameters that is being passed as inputs to the module. The parameters are RWIDTH and BWIDTH. Currently I am testing it for two cases

RWIDTH=16, BWIDTH=16 and

RWIDTH=20, BWIDTH=16

I am having some issues in making the code adapt to different width. Below is a small portion of the code.

localparam DIFF = RWIDTH-BWIDTH;
localparam BYTE_LENGTH = 8
localparam ROUND_2_BYTE = BYTE_LENGTH-DIFF;

When RWIDTH=16, BWIDTH=16 , I want ROUND_2_BYTE to be equal to 0

but when RWIDTH=20, BWIDTH=16, I want ROUND_2_BYTE to be equal to 4

Please note that ROUND_2_BYTE will be used to calculate further parameters that I have not shown for the sake of simplicity.

How can I achieve this using localparams or any other way in Verilog? I am also interested to hear about other approaches that the above can be achieved.

Solution

  • Use a conditional operator. Change:

    localparam ROUND_2_BYTE = BYTE_LENGTH-DIFF;

    to:

    localparam ROUND_2_BYTE = (DIFF == 0) ? 0 : BYTE_LENGTH-DIFF;