intel-fpga Examples and Free Source Code

Verilog module always going to default case when assigning value to input...

verilog fpga quartus intel-fpga questasim

Quartus-FPGA: Disable Path Optimization...

verilog fpga quartus intel-fpga

What is "strictly control signal" and Why is its input unconstrained?...

constraints fpga intel-fpga

Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand...

verilog quartus intel-fpga

How to add IP Libraries to Questa with Cocotb?...

intel-fpga questasim cocotb

Analyzing synchronizer MTBF in Quartus...

verilog fpga quartus intel-fpga

Inferring a True Dual Port RAM (Xilinx and Intel compatible) in Verilog...

verilog fpga xilinx intel-fpga

How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 runn...

ubuntu quartus intel-fpga

How to read data from FPGA on HPS side...

fpga intel-fpga

Timing diagram of convst. signal of ADC (ads8556)...

adc intel-fpga texas-instruments

Error: object on left-hand side of assignment must have a net type...

verilog intel-fpga

How do I concatenate parameters and integers?...

verilog system-verilog quartus intel-fpga

View report.html after DPC++ compilation for FPGA on DevCloud connected with Jupyter...

linux intel-fpga intel-oneapi dpc++

Output 'X' instead of '1' or '0' in VHDL...

vhdl quartus intel-fpga

"Serial Loader Device is missing" during Convert Programming File with Quartus Prime...

intel fpga quartus intel-fpga

How to connect module to module in Verilog?...

verilog system-verilog fpga quartus intel-fpga

How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus...

verilog system-verilog timing quartus intel-fpga

Verilog - output exuals to XXXXXXXX...

verilog fpga quartus intel-fpga

ModelSim-Altera error...

linux licensing modelsim intel-fpga quartus

How can I prevent that DSP blocks are synthesized away if they are not connected to a top level outp...

verilog fpga quartus intel-fpga

How do I load an FPGA's Registers with Data?...

verilog quartus intel-fpga

Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined...

vhdl intel-fpga quartus

NIOSII with Remote System Update IP Core for Cyclone10LP does not execute...

intel fpga intel-fpga

Intel OpenCL SDK for FPGA compile kernel for emulation with aoc command gives linker error...

opencl fpga intel-fpga

Can't compile my system in Qsys...

fpga intel-fpga nios qsys

Verilog/SystemVerilog: passing a slice of an unpacked array to a module...

verilog system-verilog fpga intel-fpga

OpenCL FPGA: Kernel Execution of 2 copies of same kernel is not being made in parallel. In addition ...

parallel-processing opencl fpga intel-fpga opencl-c

Trying to blink LED in Verilog...

verilog timing intel-fpga

Getting nan values from OpenCL FFT kernel on FPGA...

opencl fft fpga intel-fpga

Best Way to declare a LUT in OpenCL (Intel FPGA)...

opencl fpga lookup-tables intel-fpga