I am having trouble with running a Verilog project with ModelSim Student Edition 10.2c. Everything compiles without error, however I get the following error at runtime:
# vsim -gui work.testbench
# Loading work.testbench
# Loading work.circuit1_assign
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.2c/examples/circuit1_assign.v(14): Instantiation of 'OR' failed. The design unit was not found.
#
# Region: /testbench/c
# Searched libraries:
# C:/Modeltech_pe_edu_10.2c/examples/hw4
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.2c/examples/circuit1_assign.v(16): Instantiation of 'NOT' failed. The design unit was not found.
#
# Region: /testbench/c
# Searched libraries:
# C:/Modeltech_pe_edu_10.2c/examples/hw4
# ** Error: (vsim-3033) C:/Modeltech_pe_edu_10.2c/examples/circuit1_assign.v(18): Instantiation of 'AND' failed. The design unit was not found.
#
# Region: /testbench/c
# Searched libraries:
# C:/Modeltech_pe_edu_10.2c/examples/hw4
# Loading work.t1
# Error loading design
I have no idea what this means. I think this is a simple mistake I am making, but I cannot resolve it. Does anybody know what I can do so that my project will work?
I believe this has to do with the inability to include the file where AND, OR and NOT are defined. After googling, I found that the file modelsim.ini must be placed in the project directory. However, I have placed modelsim.ini in the correct directory, yet it still does not work.
I have posted all three source files for my project (which is simply testing a combinational circuit). Here is my code for circuit1_assign.v:
module circuit1_assign
(
input x,
input y,
input z,
output f
);
wire w1, w2;
OR o1 (.i0(x), .i1(y), .o(w1));
NOT n1 (.i2(z), .o(w2));
AND a1 (.i3(w1), .i4(w2), .o(f));
endmodule
Here is code for a test:
`timescale 1ns/1ps
module t1
(
output reg a,
output reg b,
output reg c
);
initial
begin
a = 0; //Do all combinations of possible input values
b = 0;
c = 0;
#10 a = 0;
#10 b = 0;
#10 c = 1;
#10 a = 0;
#10 b = 1;
#10 c = 0;
#10 a = 0;
#10 b = 1;
#10 c = 1;
#10 a = 1;
#10 b = 0;
#10 c = 0;
#10 a = 1;
#10 b = 0;
#10 c = 1;
#10 a = 1;
#10 b = 1;
#10 c = 0;
#10 a = 1;
#10 b = 1;
#10 c = 1;
#10 $finish;
end
endmodule
Here is my code for the testbench:
`timescale 1ns/1ps
module testbench();
wire l, m, n, o;
circuit1_assign c
(
.x (l),
.y (m),
.z (n),
.f (o)
);
t1 t
(
.a (l),
.b (m),
.c (n)
);
initial
begin
$monitor ($time,,"l=%b, m=%b, n=%b, o=%b",
l, m, n, o);
end
endmodule
Have you tried using lowercase gates (and, or, etc)?
In every example of gate level modelling in verilog I have seen these primitives in lowercase, not uppercase.