digital-logic Examples and Free Source Code

What's included in a Verilog always @* sensitivity list?...

verilog system-verilog digital-logic

Understanding the functioning of 'and' and 'or'...

python boolean kaggle digital-logic

Digital Logic - realizing full adder using NAND gates?...

digital-logic

How can w’xz + w’yz + x’yz’ + wxy’z be implemented with 4 NOR gates (+ inverters), given d = wyz...

digital-logic karnaugh-map nor

Using One's Complement In Place of Directly Subtracting Two Binary Numbers...

assembly cpu-architecture digital-logic

Linear feedback shift register?...

python language-agnostic digital-logic

Problem while implementing JK-Flip Flop in VHDL...

vhdl digital-logic hardware digital-design

What does the double slash(transition 0 --> 1) mean in SRAM datasheet?...

fpga digital-logic

Shifting in Verilog for multiplication...

verilog system-verilog fpga digital digital-logic

Capturing the right posedge clock in Quartus waveform...

verilog quartus test-bench digital-logic register-transfer-level

Boolean expression in SOP...

algorithm boolean boolean-expression digital-logic boolean-algebra

D-latch time diagram with preset and clear?...

cpu-architecture digital-logic flip-flop preset

Verilog Binary Coded Decimal Adder Not Outputting Correctly...

binary verilog addition digital-logic bcd

Do we use Gray Counter to avoid metastability in Asynch FIFO?...

fifo digital-logic

How to simulate output delay using next_trigger() in SystemC?...

systemc digital-logic

2's complement std_logic_vector to unsigned number...

vhdl hdl twos-complement digital-logic

How to simplify sequential logic design by eliminating nested if-else statements...

if-statement vhdl hdl digital-logic flip-flop

I don't understand how to do this Lesson :'(...

cpu-architecture circuit digital-logic

If the PC register is simultaneously read and written, does its read data contain the previous data ...

cpu-architecture digital-logic flip-flop

8 bit carry lookahead adder error with SystemVerilog in Questasim using two 4 CLA's...

verilog system-verilog digital-logic questasim

Time complexity in n bit array multiplication...

complexity-theory digital-logic

Delaying the clock by a fraction of the period...

vhdl digital-logic

Using opcodes in digital circuit design...

digital-logic

How to simplify circuits...

logic computer-science cpu-architecture circuit digital-logic

What is the output of a moore state machine?...

vhdl state-machine digital-logic

Design does not fit ispLEVER...

vhdl digital-logic digital-design

Implementation of 8:1 MUX using 3:8 decoders and 2 input gates...

cpu-architecture decoder digital-logic

Chisel3 REPL Vec assignment into module only works after eval...

chisel digital-logic

Chisel3 REPL peek value is correct but expect fails in test...

fpga chisel digital-logic

How to test modules with bundle/vec input?...

chisel digital-logic