How to wire up modules and pass value

Question

module container(x1, x2, x3, NUMBER);
input x1, x2, x3;
output NUMBER;
wire w0, w1;

dec_counter U1 (x1, x2, x3, w0, w1);
doz_counter U2 (w1, w0, NUMBER);
endmodule

module dec_counter(clk, reset, clk_enable, counter, terminal);
    input clk;
    input reset;
    input clk_enable;
    output reg [3:0] counter;
    output reg terminal;

    always @(posedge clk, posedge clk_enable, posedge reset)
        if(reset)
        begin
            terminal <= 1;
            counter <= 0;
        end
        else if(clk && clk_enable)
            if(counter < 9)
            begin
                terminal <= 1;
                counter <= counter + 1; 
            end           
            else
            begin
                terminal <= 1;
                counter <= 0;
            end  
endmodule

module doz_counter(dozens, unity, number);

input dozens;
input unity;
output reg [7:0] number;

initial begin
    number = 8'd0;
end    

always @(posedge dozens)
    if(dozens)
        number <= number + 1;

endmodule

I have module dec_counter which counts from 0 to 9. When it gets to 9+1, it shows 0 and set "output terminal" to 1. I wanted to pass that value to my next module doz_counter as "input dozens". I've tried wiring, as you can see in module container, but in my simulation, dozens is always X, even when terminal is 1.

I feel like I'm making some critical design mistakes.

Answer 1

The code you posted works fine. Refer the following figure for port connection rules. The output port can be any of reg or wire, but input port is always a wire.

A couple of mistakes are listed as follows:

You have connected an 4-bit port, reg [3:0] counter; in dec_counter module to single bit port, w0 in container module. This shall result in port connection width mismatch.

wire [3:0] w0;
wire w1;
// ...

Similarly, single bit port NUMBER in container module is connected to 8-bit port number in doz_counter module. This shall result in port connection width mismatch.

output [7:0] NUMBER;
//...

Also, the value of terminal upon reset might be zero. The if-else conditions are driving the same value of terminal. It should have different values of terminal as terminal <= 1 and terminal <= 0; respectively.

Here is a testbench for your code for reference:

module top();

bit x1, x2, x3;
bit [7:0] NUMBER;

container c(x1, x2, x3, NUMBER);

always #5 x1 = ~x1;

initial
begin
#6 x2 = 1;
#6 x2 = 0; x3 = 1;
#100 $finish;
end

endmodule