Not outputting expected value in simple assignment

Question

When I assign some value to a variable with four bits, I get an unexpected result when I simply output the value. I have never seen this before and was wondering if I'm doing something wrong syntactically.

module main;   
     reg [3:0] x;   
     initial 
     begin
         $monitor("%b",x);
         x=0010;
     end 
endmodule

I get an output of 1010. However, I expected to get an output of 0010.

Answer 1

Verilog interprets your number as decimal since you did not specify a base. The number 0010 in your Verilog code is decimal ten (10), which is 1010 in binary format. x=0010 is the same as x=10. You need to add a binary base specifier. Change:

     x=0010;

to:

     x='b0010;