quartus Examples and Free Source Code

Error (10170): HDL syntax errors in Quartus (HDL)...

verilog system-verilog hdl quartus

Array of wire OR-reduction is wrong...

verilog system-verilog quartus

Modules compiling to 0 gates...

module verilog quartus

Why is "Set as Top-Level Entity" grayed out in quartus?...

verilog system-verilog hdl quartus

Verilog module always going to default case when assigning value to input...

verilog fpga quartus intel-fpga questasim

Quartus-FPGA: Disable Path Optimization...

verilog fpga quartus intel-fpga

Quartus isn't displaying Correctly...

quartus

Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand...

verilog quartus intel-fpga

Compilation error in Quartus for Verilog language...

verilog system-verilog quartus

Analyzing synchronizer MTBF in Quartus...

verilog fpga quartus intel-fpga

Why is Modelsim displaying "Error: MIF contains illegal character" when I try to simulate?...

simulation modelsim quartus

always_comb construct does not infer purely combinational logic...

compilation verilog system-verilog quartus

How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 runn...

ubuntu quartus intel-fpga

Control signal with two buttons...

vhdl quartus

When I simulate my counter in Modelsim, the outputs are undefined...

verilog modelsim quartus

Using a macro gives errors, but putting macro text in explicitly does work...

verilog system-verilog quartus

libpng12.so.0: cannot open shared object file: wrong ELF class: ELFCLASS64...

linux docker shared-libraries quartus

7-segment display with hex output...

verilog quartus

Declaration error at define_state.h: identifier is already declared in the present scope...

verilog quartus

Attempting to make a signal high for 5 clock cycles and then remain low...

verilog system-verilog quartus

The RTL viewer in Quartus is omitting redundant gates...

verilog quartus register-transfer-level

Reset a simple counter...

verilog quartus test-bench

Why is there a difference in output when using Event Control Statement and Delay statement for a sim...

verilog simulation fpga system-verilog quartus

VHDL Error(10482) object std_logic_vector is used but not declared...

compiler-errors vhdl quartus

On left-hand side of assignment must have a variable data type...

verilog variable-assignment system-verilog quartus synthesis

$readmemh syntax error for .mif file in Verilog HDL Intel Quartus Prime...

verilog system-verilog quartus

Verilog issue with case/always statement...

verilog quartus

Why is my 8-bit counter stuck at 0 or 255?...

verilog counter quartus 8-bit cyclone

Fatal: (vsim-3807) Types do not match between component and entity for port "out1" Without...

vhdl quartus

How do I concatenate parameters and integers?...

verilog system-verilog quartus intel-fpga