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verilog

Parameter inside a module inside a module


I have read about parameters and how to redefine them at module instantiation, but what if I have a parameter inside a module inside a module? Say that I have a small module called gen:

module gen(input,output);
parameter n=2;
parameter m=10;
//do something
endmodule

That module is instantiated in another module called top:

module top(inputs,output);
gen gen1(inputs,output);
//do something
endmodule;   

I am trying to make a testbench on the big module where I need to redefine the two parameters n and m:

module tb;
reg input;
wire output;
top top1(input,output);
endmodule

How can I do that?


Solution

  • One solution is to redefine the parameters at each level:

    module gen(input,output);
    parameter n=2;
    parameter m=10;
    //do something
    endmodule
    
    
    module top(inputs,output);
    parameter n=2;
    parameter m=10;
    gen #(.n(n), .m(m)) gen1(inputs,output);
    //do something
    endmodule
    
    module tb;
    reg input;
    wire output;
    top #(.n(n), .m(m)) top1(input,output);
    endmodule
    

    Another solution is to keep your current module definition and use defparam in your testbench to hierarchically override the value of parameters:

    module tb;
    reg input;
    wire output;
    defparam top1.gen1.m = 4;
    defparam top1.gen1.n = 5;
    top top1(input,output);
    endmodule