verilog Examples and Free Source Code

Verilog's display function is giving an incorrect output?...

verilog modelsim

How to write a testbench to loop through 4 inputs?...

loops testing verilog system-verilog

How to use variables in a loop with consecutive numbers in their names?...

verilog system-verilog test-bench

How to create a string from a pre-processor macro...

macros verilog system-verilog

difference between `include and import in SystemVerilog...

verilog system-verilog vivado

How to separate by special keyword in merged associative array without other library?...

verilog system-verilog

How to print the hierarchical name of a signal given to a system-verilog task as parameter...

verilog system-verilog

If always_ff = always @ (posedge clk), then why write always_ff @ (posedge clk)?...

verilog system-verilog fpga

How to access signals in submodules with multiple modules?...

verilog system-verilog modelsim test-bench

How to define variable number of "and" gates (logic gates) programatically?...

verilog

Why does the force statement get stuck? And how to force a single bit in an array of bits?...

verilog system-verilog test-bench

How to connect a modport interface to a module that wasn't originally declared using the modport...

verilog system-verilog fpga hdl vivado

SystemVerilog Sequential Circuits Coding Style...

verilog system-verilog sequential flip-flop

Passing packed array of parameters to an array of module instances in Verilog...

arrays parameters verilog system-verilog

Getting Z values when expecting a proper output...

verilog system-verilog

Syntax error verilog defining module iverilog...

syntax-error verilog

Permuation in SystemVerilog using genvar...

verilog system-verilog vivado

Problem on HDLBits: Exams/m2014 q6c, stuck at gnd...

verilog system-verilog

In Verilog, is begin-end block really sequential ? Stratified event queue model doesn't include ...

verilog system-verilog hdl

Why do I get red color for some signals in simulation?...

verilog

Passing parameters to a Verilog function...

verilog system-verilog

verilog testbench(with for loop) for 3-8 decoder signal value not updating...

verilog

Why does this error in indexing BCD adder appear?...

for-loop indexing verilog bcd

ModelSim Simulation Stops Earlier than Expected...

verilog hdl modelsim quartus

How to connect module to module in Verilog?...

verilog system-verilog fpga quartus intel-fpga

How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus...

verilog system-verilog timing quartus intel-fpga

How do I use clocking wizard to create a slower clock for my program?...

verilog fpga vivado

Reading and writing CSV for a simple testbench...

verilog system-verilog xilinx test-bench

Real value printed with %f is 0.0000, but condition '>0' does not apply (after using $flo...

verilog system-verilog

Is the array part select +: with variable start synthesizable by Vivado?...

verilog system-verilog fpga hdl vivado