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syntax-errorverilog

Syntax error verilog defining module iverilog

I'm getting a syntax error at 11 line Full adder using xor and mux2x1

module xormux(x1, x2, x3, y1, y2);
  input x1, x2, x3;
  output y1, y2;
  wire w1, w2;

  xor gate1(w1, x1, x2);
  xor gate2(y1, w1, x3);
  mux2x1 gate3(y2, w1, x3, x2);
endmodule

module xor(output o, input i1, i2);
  assign o = i1 ^ i2;
endmodule

module mux2x1(output o, input i1, i2, s);
  assign o = s ? i2 : i1;
endmodule

Full adder using xor and mux2x1

Solution

  • xor is a reserved keyword in Verilog, per Table 22-1 in the standard (see IEEE Std 1800-2017, "22.14.2 IEEE 1364-1995 keywords").

    Use a different identifier for your module.