How to connect a modport interface to a module that wasn't originally declared using the modport

Question

I have a module that I wrote originally like so:

module design_name #(
  parameter AWIDTH = 32,
  parameter DWIDTH = 32,
  ...
  ) (
  input wire clk,
  input wire rst,
  input wire [AWIDTH-1:0] write_addr,
  ...
);
// logic, etc.
endmodule

I now, of course, want to test this block in a test bench. I want to use an interface so I have created an interface like so:

interface design_name_if #(
  parameter AWIDTH = 32,
  ...
) (
  input clk
);
  logic rst;
  logic [AWIDTH-1:0] write_addr;
  ...
  
  modport des (
    input rst,
    input write_addr,
    ...
  );
endinterface
  

I guess my question starts now; how do I use this interface in my test bench? I currently have:

module tb;

  reg clk;

  design_name_if intf (clk);

  design_name dut (
    .clk        (intf.clk),
    .rst        (intf.des.rst),
    .write_addr (intf.des.write_addr),
    ...
// I don't think the above is correct

  initial begin
    clk = 0; // or intf.clk = 0; ?
    forever #1 clk = ~clk;
  end

  initial begin
    rst = 0;
    #10
    rst = 1;
  end

endmodule

I've also tried some other simple logic, like just trying to assert certain signals and other things, but I can't even get the clk to start, nor can I ever get rst to assert when running the simulation. If it matters, the interface is declared above the tb in the same file. The module I'm testing is, probably obviously, in a different file. I can get the test bench to work without an interface by declaring all the signals as reg and wire within the test bench normally but I wanted to use an interface with tasks, functions, etc. Any help appreciated, thank you!

Answer 1

You were very close. Just get rid of the modport in the reference—a modport is not a scope, it is a set of access rights for a port connection or virtual interface reference.

 design_name dut (
    .clk        (intf.clk),
    .rst        (intf.rst),
    .write_addr (intf.write_addr),
    ...