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verilogsystem-veriloghdl

In Verilog, is begin-end block really sequential ? Stratified event queue model doesn't include any such concept


I can understand that in a begin-end block delays are addressed sequentially i.e. they are relative to previous statement. But does it mean that the begin-end block is sequential with respect to execution sequence aswell?

integer a;
initial
begin
   a = 1;          // statement_1
   $display(a);    // statement_2
   a = 2;          // statement_3
end

Since statified event queue model will put all of the above 3 statements in the Active queue of #0 timestamp. How can we assure sequential execution?


Solution

  • Answering "How can we assure sequential execution?"
    Within a begin-end block, the following applies.

    IEEE Std 1364-2005 section 11.4.1 Determinism

    "This standard guarantees a certain scheduling order:
    Statements within a begin-end block shall be executed in the order in which they appear in that begin-end block.

    Execution of statements in a particular begin-end block can be suspended in favor of other processes in the model; however, in no case shall the statements in a begin-end block be executed in any order other than that in which they appear in the source."

    The posted code should always print 1.

    For this snip, all 4 simulators on EDA Playground print 1

    module tb ();
    integer a;
    initial
    begin
       a = 1;          // statement_1
       $display(a);    // statement_2
       a = 2;          // statement_3
    end
    endmodule
    

    https://www.edaplayground.com/x/6W3Q