Passing packed array of parameters to an array of module instances in Verilog

Question

I'm having troubles with passing an array of parameters to multiple instances of the same block.

Here is my tesbench and dut (port list is simplified):

module tb_dut_top();

  
  foo_top #(
    .N_DPORT   (3),
    .N_CHAN    ({4'd2, 4'd8, 4'd0}),
    .PORT_TYPE ({2'b11, 2'b11, 2'b00})
  ) i_foo_top (
    .rstb (rstb  ),
    .clk  (clk   )
  );
  
endmodule

module foo_top #(
  parameter                     N_DPORT    = 2,
  parameter [N_DPORT-1:0][ 3:0] N_CHAN     = {N_DPORT{4'd8}},
  parameter [N_DPORT-1:0][ 1:0] PORT_TYPE  = {N_DPORT{2'b11}} 
) (
  input  rstb,
  input  clk
);

  foo_dp_top #(
    .N_CHAN        (N_CHAN[N_DPORT-1:1]          ),
    .PORT_TYPE     (PORT_TYPE[N_DPORT-1:1]       )
  ) i_foo_dp_top[N_DPORT-1:1] (

    .rstb          (rstb                ),
    .clk           (clk                 )
  );
  
endmodule

module foo_dp_top #(
  parameter [ 3:0] N_CHAN = 1,
  parameter [ 1:0] PORT_TYPE = 2'b00
) (
  input rstb,
  input clk
);

endmodule

What I want to do is to instantiate (in foo_top) N_DPORT * foo_dp_top modules (starting from 1, but also starting from 0 did not work) at once passing each of them one item of the arrays N_CHAN and PORT_TYPE.

The instance 1 gets the right value of 8 as N_CHAN, but instance 2 (I want it to get 2 as N_CHAN) keeps getting 8. It seems it propagates the first selected element of the parameter array to all the instances

I'd prefer not to use generate and for loop in order not to add extra hierarchy to the instantiated modules.

Answer 1

You cannot do this with an array of instances because the parameters must be the same for each instance—otherwise it is not really an array. This is exactly what a generate construct is for.