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veriloghdlmodelsimquartus

ModelSim Simulation Stops Earlier than Expected

I am trying to run a testbench on ModelSim. I successfully compile and analyze my circuit code with only one warning:

Warning (20028): Parallel compilation is not licensed and has been disabled

This is my testbench scenario:

initial begin
   clk = 0;
end
        
initial begin 
    forever begin
        #1; 
        clk = ~clk;
    end 
end
        
initial begin
    inc_or_res = 1;
    ld_reg8 = 1;
    #10;
        
    inc_or_res = 0;
    #90;
end

As you can see it must run for at least 100ps with the delays I defined.

Output waveform

This is the simulation result I get. As you can see, it stops at 11ps. So I can't test my scenarios. What is the reason? It doesn't give me such error in my other testbenches.

Solution

  • Ok guys I found and solved the problem.

    I was trying to implement a sequential circuit and it consists of a register for sure. The problem was I implemented this register by creating structural D flip flops and that created a combinational loop. This loop then caused the (vsim-3601) iteration limit reached error.

    Here is how a register should be implemented: https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/hdl/vlog/vlog_pro_registers.htm