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verilog

How to define variable number of "and" gates (logic gates) programatically?


I need to create 31 "and" gates, and I tried using a for loop and begin:

for(i=1;i<=30;i=i+1)
    begin
    and g[i](u[i],p[i],q[1]);  // Line 29
    end
end

But, it is showing syntax error at "and"- line 29. Is there any way it can be declared and initialised programmatically rather than declaring each "and" gate?

Screenshot of error


Solution

  • There are two other ways. You can use an array of instances

    and g[31:1](u,p, q);
    

    or you can use a generate loop

    genvar i;
    for(i=1;i<=31;i=i+1) begin : block
      and g(u[i],p[i],q[i]);
    end
    

    This creates the and gates block[1].g through block[31].g