fpga Examples and Free Source Code

non-blocking assignments with if statements...

verilog fpga

Why is there a difference in output when using Event Control Statement and Delay statement for a sim...

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Verilog with cocotb : assign statement...

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Unable to compile Micron's DDR3 memory model in Modelsim...

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Can I use a single address space for the GPU, CPU and FPGA look like to CUDA UVA?...

c++cuda shared-memory gpgpu fpga

Unable to open ftdi device with vid 0403, pid 6010...

fpga ftdi

Why this verilog assignment is wrong?...

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Convert binary input into residue number system...

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Binary to Grey Code and Grey to Binary using mode switch...

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MicroBlaze is under RESET...

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How to get access to Xilinx FPGA temperature in hdl code?...

fpga xilinx hdl vivado

My code does not move onto the next state even when the conditions are true...

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localparameters to make code generic to support different data widths...

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Passing parameters to Verilog modules...

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FFT IP Core - the results of Matlab and FFT IP Core didn't match?...

fft fpga xilinx

Clocking Block Cycle Delay Problem in SystemVerilog...

system-verilog fpga test-bench

Using keyword `all` in a sensitivity list of a clocked VHDL process...

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Should you remove all warnings in your Verilog or VHDL design? Why or why not?...

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How setup- and hold times affect the functionality of the FPGA implementation?...

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Division in Verilog and Q factor representation...

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How to change the MAC adress of FPGA ZedBoard...

fpga mac-address zynq petalinux

"Serial Loader Device is missing" during Convert Programming File with Quartus Prime...

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If always_ff = always @ (posedge clk), then why write always_ff @ (posedge clk)?...

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How to connect a modport interface to a module that wasn't originally declared using the modport...

verilog system-verilog fpga hdl vivado

How do I specify that a component within an OpenCPI application xml is within an HDL assembly?...

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Is there a way to send data from the FPGA logic on a Zedboard to an external CPU without involvement...

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VHDL - Register for Push Button...

vhdl fpga

How to connect module to module in Verilog?...

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How do I use clocking wizard to create a slower clock for my program?...

verilog fpga vivado

Is the array part select +: with variable start synthesizable by Vivado?...

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