Unable to compile Micron's DDR3 memory model in Modelsim

Question

I downloaded the memory model for the DDR3 bank that I'd be testing in simulation using Modelsim (2019.2) from Micron's website (link).

I followed the instructions from the README file to compile it, but I ran into syntax errors. I don't think Micron would make buggy code public and available to developers.

Modelsim command:

vlog +define+sg25 C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v

ERRORS

# ** Error: (vlog-13069) C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(421): near ";": syntax error, unexpected ';', expecting '('.
# ** Error: C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(424): Illegal declaration after the statement near line '421'.  Declarations must precede statements.  Look for stray semicolons.
# ** Error: (vlog-13069) C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(433): near "integer": syntax error, unexpected integer, expecting IDENTIFIER or genvar.
# ** Error: C:/Micro_projects/FPGA/hdl/micron/ddr3/ddr3.v(433): (vlog-13205) Syntax error found in the scope following 'i'. Is there a missing '::'?

initial
begin : file_io_open
    reg [BA_BITS - 1 : 0] bank;
    reg [ROW_BITS - 1 : 0] row;
    reg [COL_BITS - 1 : 0] col;
    reg [BA_BITS + ROW_BITS + COL_BITS - 1 : 0] addr;
    reg [BL_MAX * DQ_BITS - 1 : 0] data;
    string _char;                                          //LINE 421
    integer in, fio_status;

    if (!$value$plusargs("model_data+%s", tmp_model_dir))
    begin
        tmp_model_dir = "/tmp";
        $display(
            "%m: at time %t WARNING: no +model_data option specified, using /tmp.",
            $time
        );
    end

    for (integer i = 0; i < `BANKS; i = i + 1)
        memfd[i] = open_bank_file(i);

I have contacted Micron but haven't heard from them yet (it has been a few days).

Answer 1

The error is from the line which includes string, which is a SystemVerilog keyword.

You need to enable SystemVerilog syntax using the modelsim -sv option.