asic Examples and Free Source Code

Where does the third dimension (as in 4x4x4) of tensor cores come from?...

matrix gpu cpu-cores asic

Should you remove all warnings in your Verilog or VHDL design? Why or why not?...

verilog vhdl system-verilog fpga asic

Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simv...

system-verilog hdl asic

Tool for drawing timing diagrams...

hardware verilog asic timing-diagram

Why this process is executed when the simulation starts...

vhdl fpga hdl modelsim asic

Using an ASIC to brute force MD5...

hash md5 brute-force asic

What is maximum size of the Queue in SystemVerilog?...

system-verilog verification asic

Is it necessary to seperate combinational logic from sequential logic while coding in VHDL, while ai...

vhdl register-transfer-level asic soc

How can I use genvar variable to access input signals?...

verilog system-verilog fpga asic

Does enum literal deceleration of states guarantee a glitch free state machine?...

verilog system-verilog state-machine asic

Difference between process and "vanilla" VHDL...

vhdl fpga hardware asic

Why is the following clock multiplication Verilog code not working for me?...

verilog system-verilog asic soc

Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL...

vhdl synthesis asic

increasing the PPA limitation of a design...

vhdl asic

Systemc Error with the library...

c++hardware fpga systemc asic

how to track errors in FPGA/ASIC development using post place'n' route and/or post synthesis...

simulation fpga synthesis asic

Prepone Region in SystemVerilog...

system-verilog vlsi asic

Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment...

vhdl synthesis register-transfer-level asic soc

What does "quality of result (QoR)" cover?...

vhdl verilog fpga hdl asic

What's the advantage of bit over reg in systemverilog?...

system-verilog verification asic test-bench

timing for ASIC design, proper clocking for an D/A...

clock timing asic

how to write a restore reset formal test which has a long timing...

verilog system-verilog formal-languages formal-verification asic

What is the exact criteria for an inout port, when sometimes inout and output ports can be interchan...

verilog fpga system-verilog asic

What is the practical difference between implementing FOR-LOOP and FOR-GENERATE? When is it better t...

for-loop vhdl fpga hardware asic

Divide by 2 clock and corresponding reset generation...

verilog reset clock synthesis asic

Compilation error: A net is not a legal lvalue in this context...

verilog asic digital-design

synthesizable asynchronous fifo design towards an FPGA...

asynchronous verilog fpga digital asic

What if I used Asynchronous reset, Should I have to make as synchronous turned it?...

vlsi asic

Synopsys design compiler- view datapath extraction results...

vhdl synthesis asic

Area optimization for a custom library using Synopsys Design Vision...

synthesis circuit synthesizer asic