verilog Examples and Free Source Code

How to implement time delay into Verilog FSM...

time verilog delay fsm state-machine

Vivado linter: inferred latch for signal 'out_reg'...

verilog vivado synthesis

How to concatenate strings in Icarus Verilog?...

verilog system-verilog string-concatenation iverilog

Why can the argument of `uvm_info not be convert2string()?...

verilog system-verilog uvm questasim

Can I use multi-level nested generate statement?...

verilog system-verilog

How to read memory value at a specific location using VPI and verilator?...

verilog simulation system-verilog verilator vpi

using xilinx cores in modelsim via .do file...

verilog xilinx modelsim

Function returning logically incorrect values...

verilog system-verilog

Passing "type" argument to functions...

oop verilog system-verilog uvm

Verilog Coding Not Performing as Expected...

verilog register-transfer-level ice40

Casex vs Casez in Verilog...

verilog

Is it possible to let emacs verilog-auto connect wires which are templated in AUTO_TEMPLATE...

emacs verilog

Using a SystemVerilog interface as an input port to a module...

verilog system-verilog

Is it possible to delete a uvm_config_db entry?...

verilog system-verilog uvm

indexing memory for UART transmission using > 100% SLICEs Tang Nano...

verilog fpga register-transfer-level

Verilog: Is it possible to define array in generate block?...

verilog

Getting 'Z' instead of a number as the output in arithmetic_unit module in verilog...

verilog

FSM export using Yosys...

verilog fsm yosys

Illegal reference to net data in my inout datatype...

verilog hdl

What is the subtle purpose for writing Verilog code this way instead of direct continuous assignment...

verilog variable-assignment delay vivado

Optional parentheses in Verilog event control statements?...

language-lawyer verilog system-verilog

How to use XADC's GPIO on Xilinx KC705 FPGA...

verilog fpga gpio xilinx

Vivado simulation error: Iteration limit 10000 is reached...

verilog simulation

Array bit slicing...

arrays verilog system-verilog

Carry look ahead adder fails in generating proper sum and carry bits...

verilog fpga vivado

Code to generate a periodic waveform always shows output as 0...

verilog hdl

Multiple drivers conflict for unknown reason...

verilog fpga

Class object inside program block in system verilog...

class verilog system-verilog

uvm_analysis_imp vs uvm_tlm_analysis_fifo in UVM...

verilog verification uvm

N-to-1 parameterizable multiplexer code when N=1...

verilog system-verilog