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emacsverilog

Is it possible to let emacs verilog-auto connect wires which are templated in AUTO_TEMPLATE

When using AUTOINST in emacs verilog-mode auto, it will try to connect all ports listed in .v. Is it possible to let emacs verilog-mode auto only connect ports which are templated at AUTO_TEMPLATE when using AUTOWIRE / AUTOOUTPUT / AUTOINPUT ?

Solution

  • This is a great question/feature request to post at https://www.veripool.org/wiki/verilog-mode

    Mac