Illegal reference to net data in my inout datatype

Question

I am writing code in Verilog for creating a memory block capable to read and write data.

module memory( wr_n , rst_n ,data ,clk ,add , en);    

input wire wr_n;    
input wire rst_n;    
input wire clk;    
input wire en;    

parameter size = 255;    
parameter n = 7;    

inout wire [n:0] data;    
input wire [n:0] add;    

reg [n:0] mem [size:0];    
integer i;    

always @( posedge clk , negedge rst_n)    
begin    
    if(!rst_n)    
    begin        
        for( i=0; i<=size; i=i+1 )    
        begin    
            mem[i] <= 8'hff;    
        end    
    end    

    else    
    begin    
        if(en)    
        begin       
            if(!wr_n)                   //read
                data <= mem[add];    
            else                        //write
                mem[add] <= data;       
        end    
    
        else    
             data = 8'h z;    
    end      
end
endmodule 

Here when I use a continuous assignment before data, I get an error like:

"LHS in procedural assignment may not be a net:data"

even if I have declared it as wire. In my test bench I have declared data as reg type because when I declare it as net, it shows again the

"Illegal reference to net error".

I am not able to fix it.

Answer 1

There is a better way of using an inout port, it should be isolated from the logic to avoid conflicts while reading and writing, remember whenever you use inout ports make sure the points mentioned in the link are satisfied.

One such solution is declare a temporary variable for reading and writing and by using continuous assignment statement assign values to bidirectional port.

Following snippet will give you some more clearance of how the error can be avoided

reg [n:0] temp; // declare a variable and try to read and write with this variable

if(!wr_n)                   //read
  temp   <= mem[add];    
else                        //write
  mem[add] <= temp;       

  assign data = (wr_n==0)? temp : {n{1'bz}};

Remove the else part having data = 8'h z; there cannot be two else for single if statement as per LRM.