Optional parentheses in Verilog event control statements?

Question

Is the following a valid Verilog module?

module test;

logic a;

initial @a;

endmodule

Verilog simulators seem to think so -- but strictly speaking is this an extension of the official Verilog syntax?

The relevant part of the syntax of event control statements is defined as follows in the SystemVerilog-2017 standard:

event_control ::=
   @ hierarchical_event_identifier
 | @ ( event_expression )
 | @*
 | @ (*)
 | @ ps_or_hierarchical_sequence_identifier

I don't see where @a would fit into the above. The event_expression case requires parentheses, and hierarchical_event_identifier seems to be for named events and ps_or_hierarchical_sequence_identifier for sequences, whereas here a is a variable.

Answer 1

Yes, it is a valid Verilog module.

In IEEE Std 1800-2017, section 9.4.2 Event control, there is an example:

The following example shows illustrations of edge-controlled statements:

@r rega = regb; // controlled by any value change in the reg r

It shows @r, where r is a reg variable. r is considered a simplified version of a hierarchical_event_identifier without the leading dot-separated hierarchical path. Section A.9.3 Identifiers shows that hierarchical_event_identifier is the same as hierarchical_identifier, which is declared as:

hierarchical_identifier ::= [ $root . ] { identifier constant_bit_select . } identifier

Everything before the right-most identifier is optional. Annex A (normative) Formal syntax mentions:

 — Square brackets ( [ ] ) enclose optional items.
 — Braces ( { } ) enclose items that can be repeated zero or more times.