Getting 'Z' instead of a number as the output in arithmetic_unit module in verilog

Question

I'm working on a Verilog design that includes an arithmetic unit module. However, when I run a testbench for this module, I'm getting 'Z' as the output instead of the expected numerical result.

I have the following Verilog modules in my design:

module half_adder (
  input a,
  input b,
  output sum,
  output carry
);
  assign sum = a ^ b;
  assign carry = a & b;
endmodule

module full_adder (
  input a,
  input b,
  input c_in,
  output sum,
  output carry
);
  wire sum1, carry1;
  half_adder ha1 (a, b, sum1, carry1);
  half_adder ha2 (carry1, c_in, sum, carry);
endmodule

module arithmetic_unit (
  input [15:0] a,
  input [15:0] b,
  input [1:0] operation,
  output reg [31:0] result
);
  wire [15:0] sum, difference;
  wire carry_out;
  half_adder ha1 (a[0], b[0], sum[0], carry_out);
  full_adder fa1 (sum[0], a[1], b[1], sum[1], carry_out);
  full_adder fa2 (sum[1], a[2], b[2], sum[2], carry_out);
  full_adder fa16 (sum[15], a[15], b[15], sum[15], carry_out);

  always @* begin
    case(operation)
      2'b00: result <= sum;
      2'b01: result <= difference;
      2'b10: result <= a * b;
      2'b11: result <= a / b;
      default: 
        result <= 0;
    endcase
  end
endmodule




module test_arithmetic_unit;
  reg [15:0] a, b;
  reg [1:0] operation;
  wire [31:0] result;

  arithmetic_unit au (a, b, operation, result);

  initial begin
    a <= 10;
    b <= 5;
    operation <= 2'b00;
    #10;
    $display("Result: %d", result);
  end
endmodule

In the test_arithmetic_unit module, I set the inputs a to 10, b to 5, and operation to 2'b00 (addition). However, when I simulate the design and check the value of the result output, I get 'Z' instead of the expected sum.

I suspect that there might be an issue with uninitialized values or incorrect wiring in my design, but I can't seem to pinpoint the exact problem.

Could you please help me identify the cause of the 'Z' output and suggest any necessary modifications to ensure the correct numerical result is obtained?

Answer 1

If you display your result in binary or hex, you get a better picture of what is happening. In a radix other than binary, a capital Z means some of the bits of a digit are z.

%b  Result: 00000000000000000zzzzzzzzzzzz111
%h  Result: 0000ZzzZ
%d  Result: Z

You are assigning a 32-bit result from a 16-bit sum. And you have only connected sum bits 0, 1, 2, and 15.