Verilog: Is it possible to define array in generate block?

Question

How can I define an array of "register_bank" in a "generate" block and use them? I mean something like this:

genvar i;
generate
   for(i = 0; i < 4; i = i + 1)
   being
      reg [15:0] register_bank [0:31];

      always @(posedge clk)
      begin
         if(we)
         begin
            register[i][addr] <= data_i[i * 16 +: 16];
         end
         else
         begin
            data_o[i * 16 +: 16] <= register[i][addr];
         end
      end
   end
endgenerate

Answer 1

I just found the answer. We can do that using the name of the block. Just like the following code:

genvar i;
generate
   for(i = 0; i < 4; i = i + 1)
   begin : my_reg_bank
      reg [15:0] register_bank [0:31];

      always @(posedge clk)
      begin
         if(we)
         begin
            my_reg_bank[i].register_bank[addr] <= data_i[i * 16 +: 16];
         end
         else
         begin
            data_o[i * 16 +: 16] <= my_reg_bank[i].register_bank[addr];
         end
      end
   end
endgenerate