hdl Examples and Free Source Code

Is it synthesizable, using integer variable for the for-loop within a generate block in a always blo...

for-loop verilog fpga hdl generate

Bitstream Encryption...

fpga hdl vivado bitstream

Type of identifier does not agree with its usage as "boolean" type - VHDL in Quartus...

vhdl fpga identifier hdl quartus

FIR lowpass filter module error during simulation...

verilog fpga xilinx hdl vivado

I wrote this code in Verilog and there are no error messages, but it doesn't work...

verilog system-verilog hdl modelsim quartus

Verilog FSM controller and datapath...

verilog hdl fsm

First-In-First-Out (FIFO) using verilog...

memory cpu verilog cpu-architecture hdl

How does streaming operator unpacking work?...

verilog system-verilog hdl

Multiple assignments to function return value...

verilog system-verilog hdl

modelsim simulation time cycles appear to be different than test_bench...

verilog simulation fpga hdl modelsim

Best way to optionally register inputs...

verilog system-verilog hdl

Chapter 2 ALU.hdl not working on final line...

math hdl alu nand2tetris

Partitioning combination and sequential logic for reliable and low latency butterfly module for a 4 ...

verilog signal-processing fft fpga hdl

Encounter [0]: sub bus of an internal node may not be used when implementing Not16 with Not...

hardware hdl nand2tetris

No response from uut in testbench...

verilog verification hdl test-bench

Vivado stops simulation on feedback circuit...

vhdl hdl vivado

Why does the order of the lines of code not matter in Hardware Description Language?...

hdl nand2tetris

Applying Modulo To a Negative Number In Verilog...

verilog hdl

problem compiling a switch case statement in chisel...

hdl chisel

Why this process is executed when the simulation starts...

vhdl fpga hdl modelsim asic

Formal verification with Chisel...

hdl chisel formal-verification

What do the round braces do when used outside the whole non-blocking assignment?...

verilog fpga hdl

Counting the Frequency of the input on Basys2...

verilog hdl

What does `vec type 'AnonymousBundle(IO io in <module>)' must be a Chisel type, not ha...

module hdl chisel

What is the reason behind the warnings (Xst:3015) and how to rectify the same?...

verilog compiler-warnings xilinx hdl xilinx-ise

Cascading BRAM in iCE40 FPGA...

verilog fpga lattice hdl ice40

VHDL - Error comparing std_logic_vector with declared constant unsigned? The unsigned has been cast ...

vector constants vhdl hdl seven-segment-display

Why output is in unknown state?...

verilog hdl

How do i make a synthesizable parameterized encoder on Verilog?...

verilog system-verilog fpga hdl encoder-decoder

How do you write a parameterized delay register?...

verilog hdl vivado synthesis