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verilogsimulationfpgahdlmodelsim

modelsim simulation time cycles appear to be different than test_bench

i have a testbench which states at the top:

'timescale 1 ns/ 1 ps

a clock which is defined as:

code in testbench

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

run the simulation using a do file: vsim in do file

but the clock period in ModelSim waveform, when measured by the cursor, is:66ns and not 10ns clock waveform any idea?

I don't really understand what causes this behavior.

Edit: also, if i run the fallowing commands in the TESTBENCH:

initial 
begin
#1 $display("T=0t at time #1",$realtime);
#1 $display("T=0t at time #2",$realtime);
#1 $display("T=0t at time #3",$realtime);
#1 $display("T=0t at time #4",$realtime);
#2 $display("T=0t at time #5",$realtime);
end

i get:

T=1000 at time #1
T=2000 at time #2
T=3000 at time #3
T=4000 at time #4
T=6000 at time #5

I guess this is a clue, but i have no idea what causing it.

Solution

  • You should have put all the code in text form. You generate clocks following this scheme:

    always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

    So, your clocks are updated every 33 cycles: 5 + 20 + 8, which explains clock period of 66.

    An always block does not run parallel jobs, nor it restarts till it finishes. So, it will go through all updates before it starts again. As a result all your clocks will have a period of 66 and just will have an offset relative to each other.