wire output can be used as an inside variable?

Question

i am learning verilog and i am doing practice questions on https://hdlbits.01xz.net/wiki. one of the questions is:

so my answer was:

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire and_ab;
    wire and_cd;
    wire or_out;
    and(and_ab,a,b);
    and(and_cd, c, d);
    or(or_out, and_ab, and_cd);
    assign out= or_out;
    not(out_n,or_out);
endmodule

which is correct without any doubt, but their answer is:

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n );
    
    wire w1, w2;        // Declare two wires (named w1 and w2)
    assign w1 = a&b;    // First AND gate
    assign w2 = c&d;    // Second AND gate
    assign out = w1|w2; // OR gate: Feeds both 'out' and the NOT gate

    assign out_n = ~out;    // NOT gate
    
endmodule

my question is how can it be possible they use 'output' wire as an 'input' to an assign in the same module? its not reg to hold it value, not that i know if you can do it with reg as an 'output' type.

Answer 1

Verilog and SV allow the reading of outputs from within a module.
It is different than VHDL which does not allow the same.