chisel Examples and Free Source Code

Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?...

scala reduce chisel

How to propagate a value from a Module upwards...

scala chisel

In FPGA, why counter with full adder raw implementation have better clock performance than infered a...

fpga chisel yosys icestorm

How to parametrized vector of registers in chisel...

chisel

Variable sized type in Chisel...

chisel

Using Chisel Submodule within another Module: Cannot assign variables to the io input...

scala hdl chisel

Examples in Chisel that make use of MuxCase...

chisel

sbt test does not work and all the tests fail...

scala ubuntu fpga chisel rocket-chip

How to export TileLink node to LazyModule's output and generate respective verilog file...

chisel rocket-chip

Rocket Chip - Access Exception on Page Table Walk...

chisel page-tables rocket-chip

Using subrepo for Chisel project errs...

sbt chisel

Chisel : When-otherwise clause not working in function definition...

chisel

Serializer in Chisel: Register printf dont seem to make sense...

chisel chiseltest

chisel 5.0.0-RC1 and chiseltest...

sbt chisel chiseltest

How is data width determined for load/store instructions in Rocket Core?...

chisel rocket-chip instruction-encoding

Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error...

chisel rocket-chip

Exposing Simulation-only behavior in Chisel3...

chisel

Is there a simple example of how to generate verilog from Chisel3 module?...

scala sbt verilog chisel

Can Record class be used to create RegInit?...

scala chisel

using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language...

chisel rocket-chip axi4

Providing a simulation model for a chisel blackbox...

scala chisel chiseltest

Scala syntax question in Rocket-chip config.scala...

scala chisel rocket-chip

Is Chisel Counter more than 32 bits possible?...

scala counter hdl led chisel

Unable to get the RoCC accelerator built with the default Accumulator example for zed board...

riscv chisel

How to use the empty signal of the Queue?...

chisel

How to publish Chisel package?...

scala sbt chisel

Where does dut in Chisel Test get defined? (About Scala syntax)...

scala chisel chiseltest

Initializing IO with a bundle in Chisel 3.5...

chisel firrtl

Chisel how to test only one package...

chisel

Chisel memory write mask...

chisel