hdl Examples and Free Source Code

How to get access to Xilinx FPGA temperature in hdl code?...

fpga xilinx hdl vivado

Verilog Error - Quartus II - Loop Must terminate within X iterations...

verilog system-verilog hdl

My code does not move onto the next state even when the conditions are true...

verilog system-verilog hardware fpga hdl

localparameters to make code generic to support different data widths...

verilog system-verilog fpga hdl

Nand2Tetris-project5, Error: No such built-in chip used: RAM16K...

hdl nand2tetris

Verilog always block properties - sequential vs. combinatorial...

verilog hdl

How to connect a modport interface to a module that wasn't originally declared using the modport...

verilog system-verilog fpga hdl vivado

In Verilog, is begin-end block really sequential ? Stratified event queue model doesn't include ...

verilog system-verilog hdl

ModelSim Simulation Stops Earlier than Expected...

verilog hdl modelsim quartus

How is the HDL simulation timeout specified when using OpenCPI?...

simulation hdl

Is the array part select +: with variable start synthesizable by Vivado?...

verilog system-verilog fpga hdl vivado

VHDL: big slv array slicing indexed by integer (big mux)...

vhdl fpga xilinx hdl

What is the difference between these 2 counters?...

verilog system-verilog hdl

Can we disable Always block using disable statement?...

verilog system-verilog hdl

SystemVerilog calculations right before writing to clocking block...

verilog system-verilog blocking nonblocking hdl

VHDL-2008 Convert Array Width...

vhdl hdl vivado register-transfer-level

Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simv...

system-verilog hdl asic

Is Chisel Counter more than 32 bits possible?...

scala counter hdl led chisel

Two if statements in parallel assigning value to same variable in Verilog, what is the precedence th...

if-statement verilog system-verilog hdl

Four Bit Ripple Carry Adder Failing on Specific Inputs...

logic verilog hdl

Testing a 4-bit adder...

logic verilog addition hdl

Assigning the entirety of a 2D packed array to a 1D packed array with the same number of elements...

arrays system-verilog hdl register-transfer-level

wire output can be used as an inside variable?...

verilog system-verilog fpga hdl

Modifying variables inside generate statements...

verilog system-verilog hdl

This performs the Or8Way function, Why is the or1out[1] 0?...

hdl nand2tetris

SystemVerilog: Aggregate class with array of class objects...

oop verilog system-verilog hdl test-bench

Non blocking Statements execution in verilog...

verilog hdl register-transfer-level

non-blocking assignment to a variable twice in a always block gives unexpected answer...

verilog hdl

Verilog Matrix multiplication error in synthesis...

verilog xilinx hdl

What is the difference between reg and wire in a verilog module?...

verilog hdl