hdl Examples and Free Source Code

What is the difference between these 2 counters?...

verilog system-verilog hdl

Can we disable Always block using disable statement?...

verilog system-verilog hdl

SystemVerilog calculations right before writing to clocking block...

verilog system-verilog blocking nonblocking hdl

VHDL-2008 Convert Array Width...

vhdl hdl vivado register-transfer-level

Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simv...

system-verilog hdl asic

Is Chisel Counter more than 32 bits possible?...

scala counter hdl led chisel

Two if statements in parallel assigning value to same variable in Verilog, what is the precedence th...

if-statement verilog system-verilog hdl

Four Bit Ripple Carry Adder Failing on Specific Inputs...

logic verilog hdl

Testing a 4-bit adder...

logic verilog addition hdl

Assigning the entirety of a 2D packed array to a 1D packed array with the same number of elements...

arrays system-verilog hdl register-transfer-level

reg qb; cannot be driven by primitives or continuous assignment...

verilog hdl iverilog icarus

wire output can be used as an inside variable?...

verilog system-verilog fpga hdl

Modifying variables inside generate statements...

verilog system-verilog hdl

This performs the Or8Way function, Why is the or1out[1] 0?...

hdl nand2tetris

SystemVerilog: Aggregate class with array of class objects...

oop verilog system-verilog hdl test-bench

Non blocking Statements execution in verilog...

verilog hdl register-transfer-level

non-blocking assignment to a variable twice in a always block gives unexpected answer...

verilog hdl

Verilog Matrix multiplication error in synthesis...

verilog xilinx hdl

What is the difference between reg and wire in a verilog module?...

verilog hdl

Is it synthesizable, using integer variable for the for-loop within a generate block in a always blo...

for-loop verilog fpga hdl generate

Bitstream Encryption...

fpga hdl vivado bitstream

Type of identifier does not agree with its usage as "boolean" type - VHDL in Quartus...

vhdl fpga identifier hdl quartus

FIR lowpass filter module error during simulation...

verilog fpga xilinx hdl vivado

I wrote this code in Verilog and there are no error messages, but it doesn't work...

verilog system-verilog hdl modelsim quartus

Verilog FSM controller and datapath...

verilog hdl fsm

First-In-First-Out (FIFO) using verilog...

memory cpu verilog cpu-architecture hdl

How does streaming operator unpacking work?...

verilog system-verilog hdl

Multiple assignments to function return value...

verilog system-verilog hdl

modelsim simulation time cycles appear to be different than test_bench...

verilog simulation fpga hdl modelsim

Best way to optionally register inputs...

verilog system-verilog hdl