hdl Examples and Free Source Code

How do i make a synthesizable parameterized encoder on Verilog?...

verilog system-verilog fpga hdl encoder-decoder

How do you write a parameterized delay register?...

verilog hdl vivado synthesis

ALU NOOP case infers a latch: Is this OK?...

verilog hdl alu

What does [-1:0] mean in Verilog?...

verilog hdl

Simulating a CPU design written in Chisel...

simulation hdl riscv chisel

Verilog test bench for 4-bit adder with Carry Lookahead...

verilog hdl

an array declared as output reg with signals saved into multi flip-flop cannot coesist if the same a...

verilog hdl

Declaring a constant with a parameterized width...

verilog hdl parameterization

Trying to build a PC (counter) for the nand2tetris , but I'm having some trouble with the logic...

hdl nand2tetris

Using a recursive assignment inside for loop in Verilog...

verilog hdl

Passing a vector and performing operations on it results in X...

vector verilog hdl

2's complement std_logic_vector to unsigned number...

vhdl hdl twos-complement digital-logic

How to simplify sequential logic design by eliminating nested if-else statements...

if-statement vhdl hdl digital-logic flip-flop

How can i use enum in a testbench while passing a file with vectors?...

enums verilog system-verilog hdl vivado

Sorting a vector in VHDL...

vhdl hdl

How to assign a row in 2D Net in Verilog?...

verilog hdl

Verilog if statement inconsistency...

verilog hdl vivado

When to use `include in SystemVerilog...

verilog system-verilog hdl

Is it possible to use the same expression in a case statement included in different other case state...

system-verilog hdl test-bench

Behavioral Modeling is not a valid l-value in testbench.test...

verilog hdl icarus

Rewrite code using generate statement (Verilog HDL)...

verilog hdl

Add constant array element through test bench...

vhdl hdl rom test-bench

How to display data from memory file at the positive edge of the clock?...

verilog hdl test-bench

Why am I getting an inferring latch error?...

verilog system-verilog hdl vivado

The logic of designing a HDL parts from the beginning : DM...

hdl nand2tetris

What the difference between != and =/= in chisel?...

scala hdl chisel

Unknown Module Error in Verilog, but module exists already...

verilog hdl vivado

Case statements in Verilog?...

verilog hdl digital

How to pass specific array index as input in a module in Verilog?...

verilog system-verilog hdl multiplexing

How does adding 1'b1 to 8 bit reg work in Verilog?...

verilog hdl