This is an FIR lowpass filter module that uses a Kogge Stone Adder for addition. The error seems to occurs when the Kogge stone adder circuit is used. the module works fine if the kogge stone adder part is removed (line 38 -72) and if line 189(m_axis_fir_tdata <= acc0 + acc1 +...) is used instead of m_axis_fir_tdata <= res15.
This is the Kogge stone adder I am using.
This is the top module
module FIR(
input clk,
input reset,
input signed [15:0] s_axis_fir_tdata,
input s_axis_fir_tvalid,
input m_axis_fir_tready,
output reg m_axis_fir_tvalid,
output reg s_axis_fir_tready,
output reg signed [31:0] m_axis_fir_tdata
);
reg enable_fir, enable_buff;
reg [5:0] buff_cnt;
reg signed [15:0] in_sample;
reg signed [15:0] buff0, buff1, buff2, buff3, buff4, buff5, buff6, buff7, buff8, buff9, buff10, buff11, buff12, buff13, buff14, buff15,buff16;
wire signed [15:0] tap0, tap1, tap2, tap3, tap4, tap5, tap6, tap7, tap8, tap9, tap10, tap11, tap12, tap13, tap14, tap15, tap16;
reg signed [31:0] acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7, acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
wire signed [31:0] val0,val1,val2,val3,val4,val5,val6,val7,val8,val9,val10,val11,val12,val13,val14,val15,val16;
assign tap0 = -17;
assign tap1 = 62;
assign tap2 = 456;
assign tap3 = 1482;
assign tap4 = 3367;
assign tap5 = 6013;
assign tap6 = 8880;
assign tap7 = 11129;
assign tap8 = 11983;
assign tap9 = 11129;
assign tap10 = 8880;
assign tap11 = 6013;
assign tap12 = 3367;
assign tap13 = 1482;
assign tap14 = 456;
assign tap15 = 62;
assign tap16 = -17;
assign val0 = acc0;
assign val1 = acc1;
assign val2 = acc2;
assign val3 = acc3;
assign val4 = acc4;
assign val5 = acc5;
assign val6 = acc6;
assign val7 = acc7;
assign val8 = acc8;
assign val9 = acc9;
assign val10 = acc10;
assign val11 = acc11;
assign val12 = acc12;
assign val13 = acc13;
assign val14 = acc14;
assign val15 = acc15;
assign val16 = acc16;
wire [31:0] res0,res1,res2,res3,res4,res5,res6,res7,res8,res9,res10,res11,res12,res13,res14,res15;
wire carry0,carry1,carry2,carry3,carry4,carry5,carry6,carry7,carry8,carry9,carry10,carry11,carry12,carry13,carry14,carry15;
ksa_top a0(1'b0,val0,val1,res0,carry0);
ksa_top a1(carry0,res0,val2,res1,carry1);
ksa_top a2(carry1,res1,val3,res2,carry2);
ksa_top a3(carry2,res2,val4,res3,carry3);
ksa_top a4(carry3,res3,val5,res4,carry4);
ksa_top a5(carry4,res4,val6,res5,carry5);
ksa_top a6(carry5,res5,val7,res6,carry6);
ksa_top a7(carry6,res6,val8,res7,carry7);
ksa_top a8(carry7,res7,val9,res8,carry8);
ksa_top a9(carry8,res8,val10,res9,carry9);
ksa_top a10(carry9,res9,val11,res10,carry10);
ksa_top a11(carry10,res10,val12,res11,carry11);
ksa_top a12(carry11,res11,val13,res12,carry12);
ksa_top a13(carry12,res12,val14,res13,carry13);
ksa_top a14(carry13,res13,val15,res14,carry14);
ksa_top a15(carry14,res14,val16,res15,carry15);
always @ (posedge clk or negedge reset)
begin
if (reset == 1'b0)
begin
buff_cnt <= 4'd0;
enable_fir <= 1'b0;
in_sample <= 8'd0;
end
else if (m_axis_fir_tready == 1'b0 || s_axis_fir_tvalid == 1'b0)
begin
enable_fir <= 1'b0;
buff_cnt <= 6'd51;
in_sample <= in_sample;
end
else if (buff_cnt == 6'd51)
begin
buff_cnt <= 4'd0;
enable_fir <= 1'b1;
in_sample <= s_axis_fir_tdata;
end
else
begin
buff_cnt <= buff_cnt + 1;
in_sample <= s_axis_fir_tdata;
end
end
always @ (posedge clk)
begin
if(reset == 1'b0 || m_axis_fir_tready == 1'b0 || s_axis_fir_tvalid == 1'b0)
begin
s_axis_fir_tready <= 1'b0;
m_axis_fir_tvalid <= 1'b0;
enable_buff <= 1'b0;
end
else
begin
s_axis_fir_tready <= 1'b1;
m_axis_fir_tvalid <= 1'b1;
enable_buff <= 1'b1;
end
end
always @ (posedge clk)
begin
if(enable_buff == 1'b1)
begin
buff0 <= in_sample;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
buff7 <= buff6;
buff8 <= buff7;
buff9 <= buff8;
buff10 <= buff9;
buff11 <= buff10;
buff12 <= buff11;
buff13 <= buff12;
buff14 <= buff13;
buff15 <= buff14;
buff16 <= buff15;
end
else
begin
buff0 <= 0;
buff1 <= 0;
buff2 <= 0;
buff3 <= 0;
buff4 <= 0;
buff5 <= 0;
buff6 <= 0;
buff7 <= 0;
buff8 <= 0;
buff9 <= 0;
buff10 <= 0;
buff11 <= 0;
buff12 <= 0;
buff13 <= 0;
buff14 <= 0;
buff15 <= 0;
buff16 <= 0;
end
end
always @ (posedge clk)
begin
if (enable_fir == 1'b1)
begin
acc0 <= tap0 * buff0;
acc1 <= tap1 * buff1;
acc2 <= tap2 * buff2;
acc3 <= tap3 * buff3;
acc4 <= tap4 * buff4;
acc5 <= tap5 * buff5;
acc6 <= tap6 * buff6;
acc7 <= tap7 * buff7;
acc8 <= tap8 * buff8;
acc9 <= tap9 * buff9;
acc10 <= tap10 * buff10;
acc11 <= tap11 * buff11;
acc12 <= tap12 * buff12;
acc13 <= tap13 * buff13;
acc14 <= tap14 * buff14;
acc15 <= tap15 * buff15;
acc16 <= tap16 * buff16;
end
end
always @ (posedge clk)
begin
if (enable_fir == 1'b1)
begin
//m_axis_fir_tdata <= acc0 + acc1 + acc2 + acc3 + acc4 + acc5 + acc6 + acc7 + acc8 + acc9 + acc10 + acc11 + acc12 + acc13 + acc14 + acc15 + acc16;
m_axis_fir_tdata <= res15;
end
end
endmodule
this is the testbench
module tb_FIR;
reg clk, reset, s_axis_fir_tvalid, m_axis_fir_tready;
reg signed [15:0] s_axis_fir_tdata;
wire m_axis_fir_tvalid;
wire [31:0] m_axis_fir_tdata;
always begin
clk = 1; #5;
clk = 0; #5;
end
always begin
reset = 1; #20;
reset = 0; #50;
reset = 1; #1000000;
end
always begin
s_axis_fir_tvalid = 0; #100;
s_axis_fir_tvalid = 1; #1000;
s_axis_fir_tvalid = 0; #50;
s_axis_fir_tvalid = 1; #998920;
end
always begin
m_axis_fir_tready = 1; #1500;
m_axis_fir_tready = 0; #100;
m_axis_fir_tready = 1; #998400;
end
FIR FIR_i(
.clk(clk),
.reset(reset),
.s_axis_fir_tdata(s_axis_fir_tdata),
.s_axis_fir_tvalid(s_axis_fir_tvalid),
.m_axis_fir_tready(m_axis_fir_tready),
.m_axis_fir_tvalid(m_axis_fir_tvalid),
.s_axis_fir_tready(s_axis_fir_tready),
.m_axis_fir_tdata(m_axis_fir_tdata));
reg signed[15:0] mem[241:0];
initial begin
$readmemb("C:/Users/adith/docs/KTU/Verilog-FIR-master/analysis/databin.mem" , mem);
end
integer i=0;
initial begin
#15;
for(i = 0 ; i < 242 ; i = i+1) begin
s_axis_fir_tdata = mem[i];
#20;
end
end
integer file;
integer cnt=0;
initial begin
file = $fopen("dataout1.txt" , "w");
end
always @(posedge clk) begin
$fdisplay(file , m_axis_fir_tdata );
end
always @(posedge clk) begin
$display("data out (%d)------> : %d ," , cnt, m_axis_fir_tdata );
cnt = cnt + 1;
if (cnt == 250) begin
#20 $fclose(file);
reset = 0;
#20 $stop;
end
end
endmodule
these are the error messages I am getting
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/FIR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module FIR
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/black.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module black
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/grey.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module grey
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_1
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_2
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_3
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_4
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_5.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_5
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_6.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_6
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ks_7.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ks_7
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/ksa_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ksa_top
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sources_1/new/pg.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module pg
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sim_1/new/FIR_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_FIR
ERROR: [VRFC 10-2989] 's_axis_fir_tready' is not declared [C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sim_1/new/FIR_tb.v:62]
ERROR: [VRFC 10-2865] module 'tb_FIR' ignored due to previous errors [C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sim_1/new/FIR_tb.v:22]
The error message is relatively clear :
ERROR: [VRFC 10-2989] 's_axis_fir_tready' is not declared [C:/Users/adith/docs/project docs/FIR1/FIR1.srcs/sim_1/new/FIR_tb.v:62]
In FIR connexion you connected a signal that is inexistant in your testbench module :
FIR FIR_i(
.clk(clk),
.reset(reset),
.s_axis_fir_tdata(s_axis_fir_tdata),
.s_axis_fir_tvalid(s_axis_fir_tvalid),
.m_axis_fir_tready(m_axis_fir_tready),
.m_axis_fir_tvalid(m_axis_fir_tvalid),
.s_axis_fir_tready(s_axis_fir_tready), // <- s_axis_fir_tready is not declared in testbench
.m_axis_fir_tdata(m_axis_fir_tdata));