Verilog error: Range must be bounded by constant expressions

Question

I'm new to verilog and I am doing a project for my class. So here is my code:

wire [n-1:0] subcounter_of_counter;
reg [n-1:0] mask,free;
//subcounter_of_counter: dinei ena vector apo poious subcounter apoteleitai o counter(id)
always @(*) begin //command or id or mask or free or subcounter_of_counter
if (command==increment) begin
    for (int i = 0; i < n; i=i+1)begin
        if (i<id) begin
            subcounter_of_counter[i]=1'b0;
        end else if (i==id) begin
            subcounter_of_counter[i]=1'b1;
        end else begin
            if( (|mask[id+1:i]) || (|free[id+1:i]) ) begin
                subcounter_of_counter[i]=1'b0;
            end else begin
                subcounter_of_counter[i]=1'b1;
            end
        end
    end
end
end

And the error says "the range must be bounded by constant expressions."

Any ideas how else I could write it to do the same operation?

Thanks a lot

Answer 1

What you will need to do is create a masked and shifted version of mask and free.

reg [n-1:0] mask,free,local_mask, local_free;
always @(*) begin //command or id or mask or free or subcounter_of_counter
if (command==increment) begin
    local_mask = mask & ((64'b1<<id+1)-1); // clear bits above id+1
    local_free = free & ((64'b1<<id+1)-1); // clear bits above id+1
    for (int i = 0; i < n; i=i+1)begin
        if (i<id) begin
            subcounter_of_counter[i]=1'b0;
        end else if (i==id) begin
            subcounter_of_counter[i]=1'b1;
        end else begin
            if( (|local_mask) || (|local_free) ) begin
                subcounter_of_counter[i]=1'b0;
            end else begin
                subcounter_of_counter[i]=1'b1;
            end
        end
    end
local_mask = local_mask >> 1; // clear bits below i
local_free = local_free >> 1;
end // for
end // always

I didn't try this code, but hopefully it points you in the right direction.