Icarus Verilog Syntax error "I give up" for NAND gate

Question

I am getting the error message below.

./nand.v:1: syntax error
I give up.

Here is my nand.v code:

module nand (A, B, C);

    input A, B;
    output C;

    assign C = ~(A & B);

endmodule

And here is my testbench code:

`timescale 1ns / 1ns
`include "nand.v"


module nand;

reg A;
reg B;
wire C;


nand uut(A,B,C);

initial begin
    $dumpfile("nand_tb.vcd");
    $dumpvars(0, nand_tb);

    A = 0;
    B = 0;
    #20 
    A = 1; // 01
    B = 0;
    #20
    A = 0;  //10
    B = 1;
    #20
    A = 1;
    B = 1; // 11
    #20


    $display("Test complete");
end

endmodule

The error points to line 1 but I don't see why it's wrong. I am comparing the code to other .v files that I have and nothing seems out of place.

I am compiling with:

iverilog -o nand_tb.vvp nand_tb.v

I looked at other .v files that compiled successfully but I couldn't find anything wrong with my code.

Answer 1

nand is builtin to Verilog. You are getting an error you cannot define a module name or signal name with a builtin keyword. For the builtin nand the first signal in the port-list is the output, all other signals in the port-list are treated as inputs.

If you want to use the builtin nand, delete your module and update the port order.

If you want to use your nand module, you must rename it. Call it NAND or my_nand, or some other unique name.