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verilogsystem-verilogregister-transfer-level

Assign a SV port

I am wondering if this systemVerilog syntax is behaviorally correct :

module m (input [3:0] in1);
endmodule

module top();
  assign inst.in1 = 4'b1010;
 
  m inst (.in1());
  
endmodule

I am asking because I noticed some strange result when running formal logic equivalence checking. Is there another better way to drive the instance port in1 ?

Solution

  • Hierarchical references are generally not considered synthesizable.

    If you want to drive a constant into an input, you can write

    module top();
  m inst (.in1(4'b1010)); 
endmodule

    or

    module top();
  wire [3:0]  in = 4'b1010;
 
  m inst (.in1(in));
  
endmodule