How to specify AUTO_TEMPLATE wild card for inputs and outputs separately?

The common practice for auto instantiating a verilog module with wildcard is:

/* sub AUTO_TEMPLATE (
   .\(rg_.*\)   (\1_@),
); */   
sub sub
(/*AUTOINST*/);

The wildcard in the example above says "for any port name that starts with rg_ append the instance number. Note that this will be applied to both - input and output ports. Is there a way to add some kind of directive so that the above templating only applies to outputs? I found something similar here but cannot make sense of it.

Solution

This should work:

/* sub AUTO_TEMPLATE (
   .\(rg_.*\)   (@"(if (equal vl-dir \\"input\\") \\"\1\\" \\"\1_@\\")"[]),
   ); */

When the port direction (vl-dir) is an input, it will pick \1, otherwise the it will be \1_@. Note that quotes need to be \\". The [] is for auto handling bus-widths.

Other examples of @"", vl-dir, and other useful tips-and-tricks available https://veripool.org/verilog-mode/help/