Assignment to two different wires with a bit and its complement yields the same value

Question

I am currently creating a control unit for a pipelined processor using Verilog. I'm using combinatorial assignment using wires. Since I have only limited instructions to support, I have decided to just assign control signals using only limited bits.

The following is the code for the main control unit:

module mcu(
    input [5:0] Opcode,
    output ALUSrc,
    output [1:0] ALUop,
    output RegDst,
    output MemWrite,
    output MemRead,
    output MemtoReg,
    output RegWrite
    );
    
    assign ALUSrc = (Opcode[0]);
    assign ALUop[0] = (!Opcode[0]);
    assign ALUop[1] = (!Opcode[5]);
    assign RegDst = (!Opcode[0]);
    assign MemWrite = (Opcode[3]);
    assign MemRead = (!Opcode[3]);
    assign MemtoReg = (!(Opcode[0]^Opcode[1]));
    assign RegWrite = (Opcode[5]^Opcode[3]);
    
endmodule

However the ALUSrc and RegDst yields the same value despite being complements. Here is the testbench results for a sample test.

Thanks in advance for any answers.

I tried using both ! and ~, apart from which I have no clue how to fix. I've tried changing up the indexing as well, but to no avail.

Answer 1

The design issue reported in the post text, is not present in the posted code.

Here is a simple tb which drives a sequence 32'b0, 1, 2, 3 on Opcode

module tb ();
  reg [5:0] Opcode;
  reg ALUSrc;
  reg [1:0] ALUop;
  reg RegDst;
  reg MemWrite;
  reg MemRead;
  reg MemtoReg;
  reg RegWrite;
  integer i;
  
  mcu dut(
    .Opcode(Opcode),
    .ALUSrc(ALUSrc),
    .ALUop(ALUop),
    .RegDst(RegDst),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .MemtoReg(MemtoReg),
    .RegWrite(RegWrite) 
    );
  
  initial begin
    // FOR EDA PLAYGROUND $dumpfile("dump.vcd"); $dumpvars;
    $monitor("Opcode = %h, ALUSrc = %h RegDst = %h ",Opcode,ALUSrc,RegDst);
    
    for(i = 0; i < 4;i++)begin
      Opcode = i;
      #1;
    end
    
  end
endmodule

which produces the messages

xcelium> run
Opcode = 00, ALUSrc = 0 RegDst = 1 
Opcode = 01, ALUSrc = 1 RegDst = 0 
Opcode = 02, ALUSrc = 0 RegDst = 1 
Opcode = 03, ALUSrc = 1 RegDst = 0 

and these waves

using the posted code as the DUT.

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The code is behaving as expected, something else is wrong.