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parametersverilogsystem-verilog

SystemVerilog parameter override unsigned

As per IEEE-1800-2012, 23.10 Overriding module parameters :

A value parameter with a range specification, but with no type specification, shall have the range of the parameter declaration and shall be unsigned. An override value shall be converted to the type and range of the parameter.

I am wondering why the parameter shall be unsigned in this case. How is the signedness related to range?

Solution

  • All declarations of bit-level variables, parameters, and nets are by default unsigned unless you explicitly use the signed keyword. The built-in data type int/integer have the opposite signedness.

    BTW, you should be use the current IEEE 1800-2023 SystemVerilog LRM