I am a newbie with Verilog. While doing a lab assignment (yes, I've read the homework policy here), I came across a conditional statement (ternary operator).
assign w1 = load ? in : out;
I understand that assign updates whenever anything on the right changes. In this case, does assign update w1 whenever load, in, or out change? Or does assign update only when load changes?
The lab assignment is for implementing a register. This question doesn't directly relate to register implementation so I feel safe to ask for clarification here. All the documentation I've found on assign suggests that it updates whenever any operand on the right hand side changes. How does this apply with ternary operator?
Logically, the statement is equivalent to two "or-ed" "and" gates, correct ((load and in) or (~load and out))?
Thanks.
I expect assign will update only when load changes. The situation in which I'm using the statement is kinda confusing to isolate which behavior is used so I'm curious to learn from someone who knows more.
I'm also interested in understanding the logic equivalent.
Understand that there are evaluations on the right hand side and updates on the left-hand side.
An evaluation gets scheduled whenever ANY signal in the expression on the right hand side has an update. This is true for any expression with any operators. If the evaluation on the RHS causes the value on the LHS to change, then an update to the LHS gets scheduled.
In your example, if load was true and in was 0, then w1 would be driven to 0. When in updates to 1, and nothing else changed, you would want w1 to change to 1 also.
See this answer about the logic behind the ternary operator.