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verilogsystem-verilogdigital-logic

If an "else" clause is missing in a level sensitive block


If a block is level sensitive and there is a missing else clause, then what it is going to infer.


Solution

  • In a level sensitive block, if you make an assignment to any variable, you must make an assignment to that variable in all possible branches through that block. Otherwise you may infer a latch for that variable. So you really need to analyze that block to see if the missing else clause would cause a missing assignment. For example

    always_comb
       begin
       A = 0;
       if(B)
          A = C;
       end
    

    In this example, there will always be an assignment to A, so no latch inferred. Note that if you use always_comb, you should get an error if fail to make an assignment in all possible branches. (There are a few exceptions to this rule that we can save for another day)