Verilog apply force to module output without changing internal state
In my testbench, I want to simulate a system condition by forcing a certain module's output in the RTL:
force DUT.driving_module.xx = 0;
But when doing this with the force command, the wire that drives the output inside the module is also forced, which leads to other parts of the system being also affected. What I really need is to force the output of the module, without changing its internal state, like this:
I can't modify the RTL code at all. Is there a way to achieve this from the testbench?
When you have a port with a wire on both sides of the port connection, the wire gets collapsed into a single wire.
The way to do this is use logic instead of wire inside your module. The only place you should be using wire anywhere in SystemVerilog is if the signal has multiple drivers.
In Verilog, you can always make the output port of a module a reg
In either case, an output port that is a variable creates an implicit continuous assignment to whatever it connected to in the higher level module. Continuous assignments are uni-directional and a force will not propagate back into the module.
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