digital-design Examples and Free Source Code

SystemVerilog not reading data correctly...

verilog system-verilog modelsim digital-design

verilog digital digital-design

How to initialize coefficients of a large digital filter in Verilog?...

verilog signal-processing fpga vivado digital-design

How can I avoid glitches in behavioural vhdl code simulations?...

vhdl modelsim digital digital-design

Sending data from slow clock domain to fast...

fpga digital-design

Why do we have to add a "clr" (clean input wire) while forming a T flip-flop in Verilog wi...

verilog system-verilog vivado flip-flop digital-design

Writing A'B'CD+ABC' using two inverters and 5 2:1 multiplexers...

logic digital-design

Continuous assignment with 0 delay not getting the expected value after a signal positive edge...

testing system-verilog digital-design

Problem while implementing JK-Flip Flop in VHDL...

vhdl digital-logic hardware digital-design

Can somebody explain the reasoning behind decimal to binary conversion?...

binary digital-design

How can a connection between one gate input with mutiple outputs of other gates causes circuit memor...

cpu-architecture digital-design

iverilog error: syntax in assignment statement l-value...

verilog system-verilog digital-design

D FlipFlop sequence generator for the sequence 1101011 does not generate results...

verilog register-transfer-level digital-design

Design does not fit ispLEVER...

vhdl digital-logic digital-design

always block with no sensitivity list - $display not executed...

verilog digital-design

Net, which fans out, cannot be assigned more than one value...

verilog quartus digital-design

I am writing a SystemVerilog Testbench for a module that models a schematic, but don't know why ...

system-verilog digital-logic questasim digital-design

Converting six-bit binary number to it's corresponding two digit BCD number?...

digital rom bcd digital-design

Where to place the SystemVerilog interfaces, and how to name the interfaces and the files...

interface system-verilog digital-design

Verilog apply force to module output without changing internal state...

verilog simulation system-verilog register-transfer-level digital-design

"Warning C0007 : Architecture has unbound instances" issue!...

counter vhdl digital-design

How is the full adder's carry out term derived?...

addition logical-operators digital-design

How do I drive a signal from 2 sources in system verilog...

verilog system-verilog register-transfer-level vlsi digital-design

Ouput of adder module is always don't care [Verilog]...

verilog modelsim quartus digital-design

Systemverilog interfaces over hierarchical boundaries...

system-verilog digital-design

VHDL Counter returning 'X', unknown value...

binary vhdl counter vlsi digital-design

Synchronous vs Asynchronous logic - SR-Flipflop...

logic vhdl fpga flip-flop digital-design

SystemVerilog register design race avoidance...

scheduling system-verilog race-condition digital-design

Store a bitvector in flipflops instead of memory - Chisel...

memory fpga chisel flip-flop digital-design

wrong values at adder output in verilog module...

verilog vlsi digital-design