verilog Examples and Free Source Code

Delay counter not incrementing? FSM...

verilog

Add functional coverage to signal with condition...

functional-programming verilog code-coverage system-verilog

Verilog automatic task...

verilog

Division in verilog...

verilog

Problem with VCS simulation for MAC operation...

verilog

Verilog - output exuals to XXXXXXXX...

verilog fpga quartus intel-fpga

main.v:22: error: genvar is missing for generate "loop" variable 'j'...

verilog

how to declare integer variable in verilog to keep track of a value to be used in multiple for loops...

verilog vlsi

Simulation results don't match Synthesis schematics...

verilog system-verilog xilinx vivado

SystemVerilog macro through task...

macros verilog system-verilog

"A variable index into the for generate block is illegal" error...

verilog system-verilog uvm

How to turn verilog gate-level code to C++ tree representation?...

c++tree verilog

Two if statements in parallel assigning value to same variable in Verilog, what is the precedence th...

if-statement verilog system-verilog hdl

Four Bit Ripple Carry Adder Failing on Specific Inputs...

logic verilog hdl

Why is logic right shift behaving like arithmetic right shift in this code?...

verilog logical-operators

Verilog "if(test_conditional)" behavior at 'test_conditional' signal transition...

if-statement conditional-statements verilog

Procedural Assignment not supported in System Verilog...

verilog system-verilog vivado

Testing a 4-bit adder...

logic verilog addition hdl

What is the meaning of the hex value syntax with an underscore? eg:parameter FOO = 20'h0002_0...

parameters syntax verilog system-verilog

Testbench error caused by the line order of the always begin and initial begin block...

verilog system-verilog test-bench

How can I prevent that DSP blocks are synthesized away if they are not connected to a top level outp...

verilog fpga quartus intel-fpga

Verilog If else "Signal not a constant" error...

verilog fpga xilinx

How do I load an FPGA's Registers with Data?...

verilog quartus intel-fpga

The waveform of the signal does not change...

verilog iverilog

Can I assign a value to an integer with the help of another integer?...

integer verilog iverilog

The number '0' not working how I expect in Verilog...

verilog system-verilog

Verilog Data Casting...

verilog fpga vivado

Number of flip flops generated in Verilog code...

verilog system-verilog flip-flop

Debouncer in Verilog...

verilog system-verilog

Monitor class repeating forever even when simulation has reached $finish...

verilog system-verilog