main.v:22: error: genvar is missing for generate "loop" variable 'j'

Question

I have the following Verilog code for a multiplier using a carry look ahead adder. When I run that code, I get two errors. My code:

`timescale 1ns/1ps
`define DELAY 10

module cpu_wb_cla_multiplier (multicand, multiplier, product);
parameter MULTICAND_WID = 32;
parameter MULTIPLIER_WID = 32;

input [MULTICAND_WID-1:0] multicand;
input [MULTIPLIER_WID-1:0] multiplier;
output [(MULTICAND_WID + MULTIPLIER_WID - 1):0] product;

wire [MULTICAND_WID - 1:0] multicand_tmp [MULTIPLIER_WID-1:0];
wire [MULTICAND_WID - 1:0] product_tmp [MULTIPLIER_WID-1:0];
wire [MULTIPLIER_WID -1:0] carry_tmp;

generate 
 //initialize values
 for(j = 0; j < MULTIPLIER_WID; j = j + 1) begin: for_loop_j
 assign multicand_tmp[j] =  multicand & {MULTICAND_WID{multiplier[j]}};
 end
 
 assign product_tmp[0] = multicand_tmp[0];
 assign carry_tmp[0] = 1'b0;
 assign product[0] = product_tmp[0][0];
 // fpga4student.com FPGA projects, Verilog projects, VHDL projects
 for(i = 1; i < MULTIPLIER_WID; i = i + 1) begin: for_loop_i
 cpu_wb_cla_adder #(.DATA_WID(MULTIPLIER_WID)) add1 (
     
     .sum(product_tmp[i]),
     .carry_out(carry_tmp[i]),
     
   .carry_in(1'b0),
     .in1(multicand_tmp[i]),
     .in2({carry_tmp[i-1],product_tmp[i-1][31-:31]}));
 assign product[i] = product_tmp[i][0];
 end
 assign product[(MULTIPLIER_WID+MULTIPLIER_WID-1):MULTIPLIER_WID] = {carry_tmp[MULTIPLIER_WID-1],product_tmp[MULTIPLIER_WID-1][31-:31]};
endgenerate
endmodule

For this, the errors shown are:

main.v:22: error: genvar is missing for generate "loop" variable 'j'.
main.v:30: error: genvar is missing for generate "loop" variable 'i'.
2 error(s) during elaboration.

How do I fix these errors?

Answer 1

The error messages tell you that you must explicitly declare the j and i variables using the genvar keyword. You can declare them just above the generate loop, for example.

genvar j, i;

generate 
 //initialize values
 for(j = 0; j < MULTIPLIER_WID; j = j + 1) begin: for_loop_j
 // etc.

Refer to IEEE Std 1800-2017, section 27.4 Loop generate constructs:

The loop index variable shall be declared in a genvar declaration prior to its use in a loop generate scheme.