Verilog automatic task

Question

What does it mean if a task is declared with the automatic keyword in Verilog?

task automatic do_things;
  input [31:0] number_of_things;
  reg [31:0] tmp_thing;
  begin
    // ...
  end
endtask;

Note: This question is mostly because I'm curious if there are any hardware programmers on the site. :)

Answer 1

It means that the task is re-entrant - items declared within the task are dynamically allocated rather than shared between different invocations of the task.

You see - some of us do Verilog... (ugh)